Abstract: Methods, systems, and computer-storage media for target independent rasterization of an image. The target is the memory allocated for a rendered image within a graphics pipeline. Embodiments of the present invention allow the rasterization process's sampling rate to be specified independently from the memory allocated for the rendered image. Embodiments of the present invention also allow the rasterization process to be executed at a rate that does not correspond to the memory allocated for the rendered target.

Abstract: A resource used by a shader executed by a graphics processing unit is referenced using a “descriptor”. Descriptors are grouped together in memory called a descriptor heap. Applications allocate and store descriptors in descriptor heaps. Applications also create one or more descriptor tables specifying a subrange of a descriptor heap. To bind resources to a shader, descriptors are first loaded into a descriptor heap. When the resources are to be used by a set of executing shaders, descriptor tables are defined on the GPU identifying ranges within the descriptor heap. Shaders, when executing, refer to the currently defined descriptor tables to access the resources made available to them. If the shader is to be executed again with different resources, and if those resources are already in memory and specified in the descriptor heap, then the descriptor tables are changed to specify different ranges of the descriptor heap.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: A procedural texture relates texel coordinates to color values through an arbitrary function, herein called a texel shader. The procedural texture is defined by a dimension, size, texel format and the texel shader. Texel coordinates are an input to the texel shader, which generates a color value for those texel coordinates. A renderer can be implemented either in hardware, such as part of a graphics processor, or in software as a computer program executed by a processor. The renderer samples from the procedural texture in response to texel coordinates, and evaluates the texel shader on demand. Filtering also can be applied automatically to results. The results of the texel shader invocations are stored in a texture cache to take advantage of spatial and temporal locality. Results are shared among threads, processes and the like through the texture cache.

Abstract: In one embodiment, a graphics processing unit 170 may support a logical resource using a physical tile pool 350 for sparse data sets. The graphics processing unit 170 may allocate a physical memory allocation into a primary physical tile pool 350. The graphics processing unit 170 may define a mapping for a logical tile set 300 for a logical resource. The graphics processing unit 170 may selectively map a primary logical tile 320 of the logical tile set 300 to a primary physical tile 360 of the primary physical tile pool 350.

Abstract: An apparatus for training the upper extremities is taught and claimed. The invention comprises a paddle subassembly adapted to slidingly engage with a mount subassembly. A user interacts with the apparatus by pulling on a climbing hold located on the paddle subassembly. The paddle subassembly offers increasing resistance to the user, thus increasing the strength and endurance of the muscle groups exercised. Resistance elements such as, for example, bungee cords and the like are used to provide resistance. The climbing hold is interchangeable, thus allowing the use of various styles and shapes of climbing holds in order to provide a variety of strength exercises for the hands. The slide of the invention is adapted to rotate to a plurality of discrete angles. The invention is particularly useful and training the muscles of the fingers, hands, wrists and forearms in preparation for rock climbing activities.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: Mechanisms for generating an analysis result about a machine are provided. A device generates a first health management (HM) analysis result regarding a machine based on real-time first sensor information received during a first period of time and on a first version HM analytic model. The device provides, to an off-board device, a plurality of sensor information comprising the real-time first sensor information and that is generated during the first period of time. The device receives a second version HM analytic model that is based at least in part on the plurality of sensor information and fault information that identifies actual faults that have occurred on the machine. The device generates a second HM analysis result regarding the machine based on real-time second sensor information received during a second period of time and on the second version HM analytic model.

Abstract: A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: Methods, systems, and computer-storage media for target independent rasterization of an image. The target is the memory allocated for a rendered image within a graphics pipeline. Embodiments of the present invention allow the rasterization process's sampling rate to be specified independently from the memory allocated for the rendered image. Embodiments of the present invention also allow the rasterization process to be executed at a rate that does not correspond to the memory allocated for the rendered target.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering.

Abstract: An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.

Abstract: Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch.