Patents by Inventor Amar Vellanki

Amar Vellanki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190259402
    Abstract: A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.
    Type: Application
    Filed: October 25, 2018
    Publication date: August 22, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Masoud FARSHBAF ZINATI, Arun RAMANI, Amar VELLANKI, Xiaofan FEI
  • Publication number: 20190257866
    Abstract: A method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time.
    Type: Application
    Filed: September 4, 2018
    Publication date: August 22, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Gautham S. SIVASANKAR, Tejasvi DAS, Emmanuel MARCHAIS, Amar VELLANKI, Leyi YIN, John L. MELANSON, Venugopal CHOUKINISHI
  • Publication number: 20190253031
    Abstract: A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.
    Type: Application
    Filed: September 25, 2018
    Publication date: August 15, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Amar VELLANKI, Tejasvi DAS, John L. MELANSON
  • Publication number: 20190137300
    Abstract: A method may include receiving an analog modulated signal generated from a baseband signal modulated with a carrier signal wherein the baseband signal is representative of a capacitance of a capacitive sensor, converting the analog modulated signal into an equivalent digital modulated signal, demodulating the digital modulated signal to generate a demodulated digital signal representative of the capacitance of the capacitor wherein the demodulating is based, at least in part, on the carrier signal, and converting the demodulated digital signal into a digital output signal representative of a displacement of a plate of the capacitive sensor or a rate of displacement of a plate of the capacitive sensor.
    Type: Application
    Filed: March 20, 2018
    Publication date: May 9, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Amar VELLANKI, Vamsikrishna PARUPALLI, Emmanuel MARCHAIS, Zhong YOU
  • Publication number: 20190115909
    Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Tejasvi DAS, Alan Mark MORTON, Xin ZHAO, Lei ZHU, Xiaofan FEI, Johann G. GABORIAU, John L. MELANSON, Amar VELLANKI
  • Publication number: 20190115886
    Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
    Type: Application
    Filed: September 17, 2018
    Publication date: April 18, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Tejasvi DAS, Alan Mark MORTON, Xin ZHAO, Lei ZHU, Xiaofan FEI, Johann G. GABORIAU, John L. MELANSON, Amar VELLANKI
  • Patent number: 10263584
    Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 16, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Tejasvi Das, Alan Mark Morton, Xin Zhao, Lei Zhu, Xiaofan Fei, Johann G. Gaboriau, John L. Melanson, Amar Vellanki
  • Publication number: 20190056440
    Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.
    Type: Application
    Filed: March 20, 2018
    Publication date: February 21, 2019
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Amar VELLANKI, Zhong YOU, Johann G. GABORIAU
  • Patent number: 10181845
    Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 15, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Tejasvi Das, Alan Mark Morton, Xin Zhao, Lei Zhu, Xiaofan Fei, Johann G. Gaboriau, John L. Melanson, Amar Vellanki