Abstract: Methods and systems for image texture enhancement are disclosed. In some aspects, texture information for a plurality of object types is stored in a database. Objects are recognized in an image, and the type of each recognized object is identified. The database is consulted to determine textures for each of the recognized objects, based on the type of each object. A portion of a new image representing the recognized object is then updated based on its determined texture. Multiple objects having multiple different textures may be updated in this manner within a single image. This may result in improved image textures over known methods, especially when low light exposures may result in reduced image resolution and degraded textures.

Abstract: Methods and systems for image texture enhancement are disclosed. In some aspects, texture information for a plurality of object types is stored in a database. Objects are recognized in an image, and the type of each recognized object is identified. The database is consulted to determine textures for each of the recognized objects, based on the type of each object. A portion of a new image representing the recognized object is then updated based on its determined texture. Multiple objects having multiple different textures may be updated in this manner within a single image. This may result in improved image textures over known methods, especially when low light exposures may result in reduced image resolution and degraded textures.

Abstract: An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a list having a plurality of read requests. The read requests generally (i) correspond to a plurality of blocks of a reference picture and (ii) are used to decode a current picture in a bitstream carrying video. The circuit may be configured to (i) rearrange the read requests in the list based on at least one of (a) a size of a buffer in a second memory and (b) a width of a data bus of the second memory and (ii) copy a portion of the reference picture from the second memory to a third memory using one or more direct memory access transfers in response to the list.

Abstract: A digital camera system for super resolution image processing is provided. The digital camera system includes a resolution enhancement module configured to receive at least a portion of an image, to increase the resolution of the received image, and to output a resolution enhanced image and an edge extraction module configured to receive the resolution enhanced image, to extract at least one edge of the resolution enhanced image, and to output the extracted at least one edge of the resolution enhanced image, the at least one edge being a set of contiguous pixels where an abrupt change in pixel values occur. The digital camera system also includes an edge enhancement module configured to receive the resolution enhanced image and the extracted at least one edge, and to combine the extracted at least one edge or a derivation of the extracted at least one edge with the resolution enhanced image.

Abstract: A digital camera system for super resolution image processing constructed to receive a plurality of input frames and output at least one digitally zoomed frame is provided. The digital camera system includes a motion registration module configured to generate motion information associated with the plurality of input frames, an interpolation module configured to generate a plurality of interpolated input frames based at least in part on the plurality of input frames and the motion information, a weights calculation module configured to calculate one or more weights associated with the plurality of input frames based on at least the motion information, and a weighted merging module configured to merge the plurality interpolated input frames consistent with the one or more weights to generate the at least one digitally zoomed frame.

Abstract: A digital camera system for super resolution image processing is provided. The digital camera system includes a resolution enhancement module configured to receive at least a portion of an image, to increase the resolution of the received image, and to output a resolution enhanced image and an edge extraction module configured to receive the resolution enhanced image, to extract at least one edge of the resolution enhanced image, and to output the extracted at least one edge of the resolution enhanced image, the at least one edge being a set of contiguous pixels where an abrupt change in pixel values occur. The digital camera system also includes an edge enhancement module configured to receive the resolution enhanced image and the extracted at least one edge, and to combine the extracted at least one edge or a derivation of the extracted at least one edge with the resolution enhanced image.

Abstract: A digital camera system for super resolution image processing is provided. The digital camera system includes a resolution enhancement module configured to receive at least a portion of an image, to increase the resolution of the received image, and to output a resolution enhanced image and an edge extraction module configured to receive the resolution enhanced image, to extract at least one edge of the resolution enhanced image, and to output the extracted at least one edge of the resolution enhanced image, the at least one edge being a set of contiguous pixels where an abrupt change in pixel values occur. The digital camera system also includes an edge enhancement module configured to receive the resolution enhanced image and the extracted at least one edge, and to combine the extracted at least one edge or a derivation of the extracted at least one edge with the resolution enhanced image.

Abstract: A digital camera system for super resolution image processing constructed to receive a plurality of input frames and output at least one digitally zoomed frame is provided. The digital camera system includes a motion registration module configured to generate motion information associated with the plurality of input frames, an interpolation module configured to generate a plurality of interpolated input frames based at least in part on the plurality of input frames and the motion information, a weights calculation module configured to calculate one or more weights associated with the plurality of input frames based on at least the motion information, and a weighted merging module configured to merge the plurality interpolated input frames consistent with the one or more weights to generate the at least one digitally zoomed frame.

Abstract: An apparatus having a memory and a circuit is disclosed. The memory may be configured to store a picture being encoded. The circuit may be configured to calculate a plurality of first arrays directly from a plurality of neighboring samples around a current block of the picture. Each first array generally represents a respective one of a plurality of intra-prediction modes. Each first array may be spatially smaller than the current block. The circuit may also be configured to calculate a second array from a plurality of current samples in the current block. The second array may spatially match the first arrays. The circuit may be further configured to generate a plurality of scores of the intra-prediction modes by comparing the first arrays with the second array and select a given one of the intra-prediction modes corresponding to a lowest of the scores to encode the current block.

Abstract: A digital camera system for super resolution image processing is provided. The digital camera system includes a resolution enhancement module configured to receive at least a portion of an image, to increase the resolution of the received image, and to output a resolution enhanced image and an edge extraction module configured to receive the resolution enhanced image, to extract at least one edge of the resolution enhanced image, and to output the extracted at least one edge of the resolution enhanced image, the at least one edge being a set of contiguous pixels where an abrupt change in pixel values occur. The digital camera system also includes an edge enhancement module configured to receive the resolution enhanced image and the extracted at least one edge, and to combine the extracted at least one edge or a derivation of the extracted at least one edge with the resolution enhanced image.

Abstract: An apparatus having a cache and a processor. The cache may be configured to (i) buffer a first subset of reference samples of a reference picture to facilitate a motion estimation of a current block and (ii) prefetch a second subset of the reference samples while a first search pattern is being tested. The first search pattern used in the motion estimation generally defines multiple motion vectors to test. The reference samples of the second subset may be utilized by a second search pattern in the motion estimation of the current block. The prefetch of the second subset may be based on a geometry of the first search pattern and scores of the motion vectors already tested. The processor may be configured to calculate the scores of the motion vectors by a block comparison of the reference samples to the current block according to the first search pattern.

Abstract: An apparatus comprising a buffer and a processor. The buffer may be configured to store a plurality of fetch sets. The processor may be configured to perform a change of flow operation based upon at least one of (i) a comparison between addresses of two memory locations involved in each of two memory accessess, (ii) a first predefined prefix code, and (iii) a second predefined prefix code.

Abstract: An apparatus having a first circuit and a plurality of second circuits is disclosed. The first circuit may be configured to dispatch a plurality of sets in a sequence. Each set generally includes a plurality of instructions. The second circuits may be configured to (i) execute the sets during a plurality of execution cycles respectively and (ii) stop the execution in a particular one of the second circuits during one or more of the execution cycles in response to an expiration of a particular counter that corresponds to the particular second circuit.

Abstract: An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a list having a plurality of read requests. The read requests generally (i) correspond to a plurality of blocks of a reference picture and (ii) are used to decode a current picture in a bitstream carrying video. The circuit may be configured to (i) rearrange the read requests in the list based on at least one of (a) a size of a buffer in a second memory and (b) a width of a data bus of the second memory and (ii) copy a portion of the reference picture from the second memory to a third memory using one or more direct memory access transfers in response to the list.

Abstract: An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.

Abstract: An apparatus having a cache and a processor is disclosed. The cache may be configured to (i) buffer a first subset of a reference picture to facilitate a motion estimation of a current block at a first level of a hierarchical motion estimation and (ii) prefetch a second subset of the reference picture to the cache in response to an occurrence of a condition before the motion estimation is completed at the first level. The processor may be configured to calculate a plurality of scores by comparing the current block with the first subset of the reference picture. The second subset generally (i) resides at a second level of the hierarchical motion estimation and (ii) may be determined from the scores calculated prior to the occurrence of the condition.

Abstract: An apparatus having a cache and a processor. The cache may be configured to (i) buffer a first subset of reference samples of a reference picture to facilitate a motion estimation of a current block and (ii) prefetch a second subset of the reference samples while a first search pattern is being tested. The first search pattern used in the motion estimation generally defines multiple motion vectors to test. The reference samples of the second subset may be utilized by a second search pattern in the motion estimation of the current block. The prefetch of the second subset may be based on a geometry of the first search pattern and scores of the motion vectors already tested. The processor may be configured to calculate the scores of the motion vectors by a block comparison of the reference samples to the current block according to the first search pattern.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) receive two input signals. Each input signal generally carries a respective data value. Each data value may have a respective sign bit and a respective at least one guard bit. The first circuit may also be configured to (ii) scale each data value independently such that all of the respective guard bits have a same value as the respective sign bit and (iii) generate a product value in an output signal by adjusting an intermediate value based on the scaling of the data values. The second circuit may be configured to generate the intermediate value by multiplying the two data values as scaled.

Abstract: An apparatus having a memory and a circuit is disclosed. The memory may be configured to store a picture being encoded. The circuit may be configured to calculate a plurality of first arrays directly from a plurality of neighboring samples around a current block of the picture. Each first array generally represents a respective one of a plurality of intra-prediction modes. Each first array may be spatially smaller than the current block. The circuit may also be configured to calculate a second array from a plurality of current samples in the current block. The second array may spatially match the first arrays. The circuit may be further configured to generate a plurality of scores of the intra-prediction modes by comparing the first arrays with the second array and select a given one of the intra-prediction modes corresponding to a lowest of the scores to encode the current block.

Abstract: A method for performing motion estimation based on at least a first VOP stored in a memory includes the steps of: receiving a request to read a data block indicative of at least a portion of the first VOP for predicting a second VOP that is temporally adjacent to the first VOP; utilizing a DMA module for determining whether the data block is a UMV block; translating a block address for retrieving at least a portion of the data block from the memory as a function of one or more parameters generated by the DMA module; and generating a complete data block as a function of the portion of the data block retrieved from the memory and the one or more parameters generated by the DMA module.