Patents by Inventor Amir Mezer
Amir Mezer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220360359Abstract: Examples described herein relate to a network interface device that includes first circuitry to perform a first scrambling operation on input data; second circuitry to perform a second scrambling operation on the input data; and third circuitry to select the second scrambled input data based on the first scrambled input data including a data sequence that is associated with receiver malfunction and the second scrambled input data including the data sequence that is associated with receiver malfunction.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Alon MEISLER, Ehud SHOOR, Amir MEZER, Tsion VIDAL
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Patent number: 11190208Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: GrantFiled: June 18, 2020Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Patent number: 10924132Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: GrantFiled: September 8, 2017Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Publication number: 20200321978Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Patent number: 10498469Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.Type: GrantFiled: May 21, 2018Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Mor Cohen, Amir Mezer, Golan Perry, Adee Ofir Ran
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Publication number: 20190215008Abstract: Computing devices and techniques for providing link partner health reporting are described. In one embodiment, for example, an apparatus may include at least one memory, and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a plurality of error counters, each of the plurality of error counters associated with a number of errors, determine the number of errors for each data unit of a plurality of data units associated with a data block, increment each of the plurality of error counters corresponding with the number of errors for each data unit of the plurality of data units, provide a plurality of error counts for the data block to a link partner, the plurality of error counts corresponding to the number of errors accumulated in each of the plurality of error counters for the data block, and reset the plurality of error counters. Other embodiments are described and claimed.Type: ApplicationFiled: September 8, 2017Publication date: July 11, 2019Applicant: Intel CorporationInventors: Adee Ofir Ran, Amir Mezer, Alon Meisler, Assaf Benhamou, Itamar Levin, Yoni Landau
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Publication number: 20190044627Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.Type: ApplicationFiled: May 21, 2018Publication date: February 7, 2019Inventors: Mor COHEN, Amir MEZER, Golan PERRY, Adee Ofir RAN
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Patent number: 9374202Abstract: A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ratio determined for a device.Type: GrantFiled: March 15, 2013Date of Patent: June 21, 2016Assignee: Intel CorporationInventors: Adee O. Ran, Amir Mezer, Ophir Gazinski, Sanjay R. Ravi, David G. Ellis, Stephen J. Peters, Jeffrey M. Shuey
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Publication number: 20140281763Abstract: A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Adee O. Ran, Amir Mezer, Ophir Gazinski, Sanjay R. Ravi, David G. Ellis, Stephen J. Peters, Jeffrey M. Shuey
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Patent number: 8644371Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.Type: GrantFiled: December 28, 2012Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Amir Mezer, Adee Ran
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Publication number: 20130136161Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.Type: ApplicationFiled: December 28, 2012Publication date: May 30, 2013Inventors: Amir Mezer, Adee Ran
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Patent number: 8422891Abstract: Jitter reduction of electrical signals from limiting optical modules is described. In one example, a process includes receiving an amplitude limited electrical signal that has been converted from an optical signal, applying a filter to the received electrical signal, measuring an indication of jitter of the filtered signal, and selecting parameters of the linear filter based on the measured indication.Type: GrantFiled: September 24, 2010Date of Patent: April 16, 2013Assignee: Intel CorporationInventors: Amir Mezer, Ehud Shoor
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Patent number: 8379710Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.Type: GrantFiled: March 10, 2009Date of Patent: February 19, 2013Assignee: Intel CorporationInventors: Amir Mezer, Adee Ran
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Patent number: 8300679Abstract: According to some embodiments, a digital switching distortion canceller may receive Ethernet data along with an Ethernet class AB transceiver switching signal. A combiner may combine the output of the digital switching distortion canceller with a digital high switching distortion signal to generate a corrected output signal. According to other embodiments, a switching-signal-to-voltage-converter receives an Ethernet class AB transceiver switching signal and generates a common-mode compensation voltage adjustment. An analog combiner may combine the common-mode compensation voltage adjustment with a noisy common-mode signal to generate a stabilized common-mode voltage. Note that reduction of switching-related distortion might be achieved in the digital domain, in the analog domain, or in both domains according to the embodiments described herein.Type: GrantFiled: December 29, 2008Date of Patent: October 30, 2012Assignee: Intel CorporationInventor: Amir Mezer
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Patent number: 8175823Abstract: A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.Type: GrantFiled: December 17, 2008Date of Patent: May 8, 2012Assignee: Intel CorporationInventors: Amir Mezer, Assaf Benhamou
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Publication number: 20120076508Abstract: Jitter reduction of electrical signals from limiting optical modules is described. In one example, a process includes receiving an amplitude limited electrical signal that has been converted from an optical signal, applying a filter to the received electrical signal, measuring an indication of jitter of the filtered signal, and selecting parameters of the linear filter based on the measured indication.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: Amir Mezer, Ehud Shoor
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Patent number: 8130939Abstract: In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceller to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceller. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2007Date of Patent: March 6, 2012Assignee: Intel CorporationInventors: Amir Mezer, Adee Ran, Ehud Shoor, Harry Birenboim, Yaniv Hadar, Assaf Benhamou
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Patent number: 8102960Abstract: A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors.Type: GrantFiled: March 28, 2008Date of Patent: January 24, 2012Assignee: Intel CorporationInventors: Adee Ran, Ehud Shoor, Amir Mezer
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Patent number: 7920649Abstract: In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be controlled to perform a timing recovery mechanism that implements a Mueller and Müller (MM)-based algorithm to generate a sensor output responsive to the digitized signal, where the incoming signal is non-linearly precoded in a transmitter from which the signal is received. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2007Date of Patent: April 5, 2011Assignee: Intel CorporationInventors: Ehud Shoor, Adee Ran, Amir Mezer
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Patent number: 7823041Abstract: Techniques are described herein that can be used to decode signals received over multiple channels. The received signals may be processed using noise reducing logic. Signal-to-noise ratio information per channel for signals received over each of the multiple channels may be considered to determine reliability information concerning the slicer input for each channel. Low density parity check codes or other forward error correction (FEC) codes may be used to decode the processed signals from all the multiple channels based on the reliability information.Type: GrantFiled: September 18, 2006Date of Patent: October 26, 2010Assignee: Intel CorporationInventors: Amir Mezer, Harry Birenboim