Patents by Inventor Amir Mezer

Amir Mezer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100232492
    Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 16, 2010
    Inventors: Amir Mezer, Adee Ran
  • Publication number: 20100166125
    Abstract: According to some embodiments, a digital switching distortion canceller may receive Ethernet data along with an Ethernet class AB transceiver switching signal. A combiner may combine the output of the digital switching distortion canceller with a digital high switching distortion signal to generate a corrected output signal. According to other embodiments, a switching-signal-to-voltage-converter receives an Ethernet class AB transceiver switching signal and generates a common-mode compensation voltage adjustment. An analog combiner may combine the common-mode compensation voltage adjustment with a noisy common-mode signal to generate a stabilized common-mode voltage. Note that reduction of switching-related distortion might be achieved in the digital domain, in the analog domain, or in both domains according to the embodiments described herein.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Inventor: Amir Mezer
  • Patent number: 7747292
    Abstract: Techniques to perform adaptive interference cancellation are described. A first apparatus may include a timing recovery module to produce a timing recovery command signal, an interference canceller to receive an interference reference signal and produce an interference canceller signal, and an interpolator to couple to the timing recovery module and the interference canceller, the interpolator to receive the timing recovery command signal and the interference canceller signal and produce an interpolated interference canceller signal. A second apparatus may include a time-domain interference canceller to receive an interference reference signal and produce a time-domain interference canceller signal and a frequency-domain interference canceller to receive the interference reference signal and produce a frequency-domain interference canceller signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: June 29, 2010
    Assignee: Intel Corporation
    Inventors: Amir Mezer, Yaniv Hadar, Ehud Shoor
  • Publication number: 20100153032
    Abstract: A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Inventors: Amir Mezer, Assaf Benhamou
  • Patent number: 7724847
    Abstract: Techniques are described to reduce delayed reflection inter-symbol interference (ISI) in signals. In some implementations, a channel reflection canceller is provided at a signal receiver to reduce delayed reflection ISI in received signals. The channel reflection canceller may be provided with a signal from an equalizer output or a tentative or final decision from a forward-error correction (FEC) decoder. Based on the signal from the equalizer output or tentative or final decisions from the FEC decoder, the channel reflection canceller may generate a signal to reduce delayed reflection ISI in received signals. In addition or as an alternative, in some implementations, the remote transmitter of the signal generates a delayed reflection ISI reducing signal to reduce delayed reflection ISI present in the signal transmitted over a channel. The transmitter may generate the delayed reflection ISI reducing signal using information provided by the remote signal receiver.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Baruch Bublil, Amir Mezer
  • Patent number: 7693240
    Abstract: A system, apparatus, method and article to converge a communications system receiver are described. The apparatus may include an interference canceller to receive an interference signal and to produce an adaptive signal. The interference canceller is adapted by a first adaptation module. An equalizer is coupled to the interference canceller. The interference canceller is located before the equalizer. The equalizer receives an input signal formed of a sum of a received input signal and the adaptive signal. A slicer is coupled to the equalizer and to the interference canceller. The slicer receives an equalized version of equalizer coefficients and produces a slicer error. The first adaptation module adapts the interference canceller utilizing a convolution of the interference signal with the equalizer coefficients, and multiplying the results by the slicer error. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Amir Mezer, Alex Sokolovsky
  • Publication number: 20100014566
    Abstract: A 10GBase-T Small Form Factor Pluggable (SFP+) module. The 10GBase-T SFP+ module has a 10GBase-T physical layer (PHY) module with a communication interface and an interface module with SFP+ high speed serial electrical interface (SFI). During receive operation, 10GBase-T data is received from a link partner via the communication interface. The 10GBase-T PHY module processes the 10GBase-T data into intermediate data. The interface module receives the intermediate data from the 10GBase-T PHY module, processes the intermediate data into 10GBase-R data, and outputs the 10GBase-R data to a SFI host via the SFI. During transmit operation, 10GBase-R data is transmitted by a SFI host via the SFI. The interface module processes the 10GBase-R data into intermediate data. The 10GBase-T PHY receives the intermediate data from the interface module, processes the intermediate data into 10GBase-T data, and outputs the 10GBase-T data to a link partner via the communication interface.
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Inventors: Amir Mezer, Adee Ofir Ran
  • Publication number: 20090245448
    Abstract: A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: Adee Ran, Ehud Shoor, Amir Mezer
  • Patent number: 7567517
    Abstract: In one embodiment of the present invention, a method includes establishing a communication link between a first link partner and a second link partner, causing the first link partner to transmit idle signals, and analyzing a desired channel of the communication link using the idle signals. As an example, the communication link may be an Ethernet link and the link may be maintained during the channel analysis so that system data transmissions may be resumed or initiated immediately after the analysis is completed.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventor: Amir Mezer
  • Patent number: 7492292
    Abstract: In one embodiment, the present invention includes an apparatus having an analog front end to receive a signal from a communication channel physical medium, an analog-to-digital converter (ADC) coupled to an output of the analog front end to digitize the received signal, and a digital signal processor (DSP) coupled to receive an output signal of the ADC and to process the digitized signal to generate a decision output and an error signal, and a feedback path to provide the error signal from the DSP to the ADC for use in calibration. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Amir Mezer, Alon Meisler
  • Publication number: 20080297383
    Abstract: In one embodiment, the present invention includes an apparatus having an analog front end to receive a signal from a communication channel physical medium, an analog-to-digital converter (ADC) coupled to an output of the analog front end to digitize the received signal, and a digital signal processor (DSP) coupled to receive an output signal of the ADC and to process the digitized signal to generate a decision output and an error signal, and a feedback path to provide the error signal from the DSP to the ADC for use in calibration. Other embodiments are described and claimed.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Inventors: Amir Mezer, Alon Meisler
  • Publication number: 20080240318
    Abstract: In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be controlled to perform a timing recovery mechanism that implements a Mueller and Müller (MM)-based algorithm to generate a sensor output responsive to the digitized signal, where the incoming signal is non-linearly precoded in a transmitter from which the signal is received. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Ehud Shoor, Adee Ran, Amir Mezer
  • Publication number: 20080240412
    Abstract: In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceler to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceler. Other embodiments are described and claimed.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Amir Mezer, Adee Ran, Ehud Shoor, Harry Birenboim, Yaniv Hadar, Assaf Benhamou
  • Publication number: 20080144588
    Abstract: A wireless communication device and a method and of prioritizing services in a wireless local area network is provided. The method includes defining a first priority of a first service of a first basic service set of a wireless local area network and defining a second priority of a second service of a second basic service set of the wireless local area network, wherein the first priority is different from the second priority.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 19, 2008
    Inventors: Amir Mezer, Amit Barak
  • Publication number: 20080096512
    Abstract: Techniques to perform adaptive interference cancellation are described. A first apparatus may include a timing recovery module to produce a timing recovery command signal, an interference canceller to receive an interference reference signal and produce an interference canceller signal, and an interpolator to couple to the timing recovery module and the interference canceller, the interpolator to receive the timing recovery command signal and the interference canceller signal and produce an interpolated interference canceller signal. A second apparatus may include a time-domain interference canceller to receive an interference reference signal and produce a time-domain interference canceller signal and a frequency-domain interference canceller to receive the interference reference signal and produce a frequency-domain interference canceller signal. Other embodiments are described and claimed.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 24, 2008
    Inventors: Amir Mezer, Yaniv Hadar, Ehud Shoor
  • Publication number: 20080069052
    Abstract: Techniques are described herein that can be used to decode signals received over multiple channels. The received signals may be processed using noise reducing logic. Signal-to-noise ratio information per channel for signals received over each of the multiple channels may be considered to determine reliability information concerning the slicer input for each channel. Low density parity check codes or other forward error correction (FEC) codes may be used to decode the processed signals from all the multiple channels,based on the reliability information.
    Type: Application
    Filed: September 18, 2006
    Publication date: March 20, 2008
    Inventors: Amir Mezer, Harry Birenboim
  • Publication number: 20080056408
    Abstract: Apparatus, systems, and methods are provided to provide analog pre-equalization to a signal received from a communication channel prior to analog-to-digital conversion of the signal.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 6, 2008
    Inventor: Amir Mezer
  • Publication number: 20070237270
    Abstract: A system, apparatus, method and article to converge a communications system receiver are described. The apparatus may include an interference canceller to receive an interference signal and to produce an adaptive signal. The interference canceller is adapted by a first adaptation module. An equalizer is coupled to the interference canceller. The interference canceller is located before the equalizer. The equalizer receives an input signal formed of a sum of a received input signal and the adaptive signal. A slicer is coupled to the equalizer and to the interference canceller. The slicer receives an equalized version of equalizer coefficients and produces a slicer error. The first adaptation module adapts the interference canceller utilizing a convolution of the interference signal with the equalizer coefficients, and multiplying the results by the slicer error. Other embodiments are described and claimed.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Inventors: Amir Mezer, Alex Sokolovsky
  • Patent number: 7239665
    Abstract: In some embodiments, a method includes determining a characteristic of a communication channel and selecting, on the basis of the determined characteristic, a pre-computed equalizer characteristic for application to signals received via the communication channel.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventor: Amir Mezer
  • Publication number: 20060251194
    Abstract: Techniques are described to reduce delayed reflection inter-symbol interference (ISI) in signals. In some implementations, a channel reflection canceller is provided at a signal receiver to reduce delayed reflection ISI in received signals. The channel reflection canceller may be provided with a signal from an equalizer output or a tentative or final decision from a forward-error correction (FEC) decoder. Based on the signal from the equalizer output or tentative or final decisions from the FEC decoder, the channel reflection canceller may generate a signal to reduce delayed reflection ISI in received signals. In addition or as an alternative, in some implementations, the remote transmitter of the signal generates a delayed reflection ISI reducing signal to reduce delayed reflection ISI present in the signal transmitted over a channel. The transmitter may generate the delayed reflection ISI reducing signal using information provided by the remote signal receiver.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 9, 2006
    Inventors: Baruch Bublil, Amir Mezer