Patents by Inventor Amir Nahir
Amir Nahir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10983887Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.Type: GrantFiled: December 6, 2019Date of Patent: April 20, 2021Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
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Publication number: 20200151074Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.Type: ApplicationFiled: December 6, 2019Publication date: May 14, 2020Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
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Patent number: 10528443Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.Type: GrantFiled: January 30, 2015Date of Patent: January 7, 2020Assignees: SAMSUNG ELECTRONICS CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
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Patent number: 10387208Abstract: A method comprising, in a cloud computing system: receiving a new job at the cloud computing system; sampling VMs (Virtual Machines) of the cloud computing system for the load currently handled by each of the VMs; if the load currently handled by the VMs is within operational bounds, sending the new job to one of the VMs which currently handles the highest load compared to other ones of the VMs; and if the load currently handled by the VMs is beyond operational bounds, sending the new job to one of the VMs which currently handles the lowest load compared to other ones of the VMs.Type: GrantFiled: July 14, 2015Date of Patent: August 20, 2019Assignee: Technion Research & Development Foundation LimitedInventors: Amir Nahir, Ariel Orda, Dan Raz
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Patent number: 9852037Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: GrantFiled: December 22, 2016Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: James N. Klazynski, Amir Nahir
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Patent number: 9804911Abstract: A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.Type: GrantFiled: May 27, 2015Date of Patent: October 31, 2017Assignee: APPLE INC.Inventors: Amir Nahir, Randal S. Thelen, Yair Dagan, Yuval Gonczarowski
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Patent number: 9678151Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: GrantFiled: August 25, 2016Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: James N. Klazynski, Amir Nahir
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Patent number: 9626267Abstract: A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.Type: GrantFiled: January 30, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
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Patent number: 9626265Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: GrantFiled: June 29, 2015Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: James N. Klazynski, Amir Nahir
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Publication number: 20170103008Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: James N. Klazynski, Amir Nahir
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Patent number: 9569345Abstract: Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.Type: GrantFiled: December 27, 2013Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin
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Publication number: 20160378581Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: ApplicationFiled: February 2, 2016Publication date: December 29, 2016Inventors: James N. Klazynski, Amir Nahir
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Publication number: 20160377680Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: ApplicationFiled: August 25, 2016Publication date: December 29, 2016Inventors: James N. Klazynski, Amir Nahir
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Publication number: 20160378626Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: James N. Klazynski, Amir Nahir
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Patent number: 9513985Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.Type: GrantFiled: February 2, 2016Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: James N. Klazynski, Amir Nahir
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Publication number: 20160350163Abstract: A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.Type: ApplicationFiled: May 27, 2015Publication date: December 1, 2016Inventors: Amir Nahir, Randal S. Thelen, Yair Dagan, Yuval Gonczarowski
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Publication number: 20160224452Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone then a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
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Publication number: 20160224448Abstract: A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
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Patent number: 9337845Abstract: A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.Type: GrantFiled: June 16, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Ilia Averbouch, Oded Margalit, Amir Nahir, Yehuda Naveh, Gil Shurek
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Patent number: 9251045Abstract: Localizing errors by: (i) running a testcase on a hardware processor and saving results; (ii) running the testcase on a software model of the processor and saving results; (iii) recording control flow information during the software run; (iv) determining a set of miscompare data storage locations by comparing the results from the hardware run with those from the software run; (v) based on the set of miscompare data storage locations and/or the control flow information, generating and running a modified version of the testcase that takes a different execution path when run on the software model than did the original testcase when run on the software model; and (vii) comparing the results from the hardware run and the results obtained from the modified software run to provide an indication of similarity between execution paths taken in these respective runs.Type: GrantFiled: February 26, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin