Patents by Inventor Amir Nahir
Amir Nahir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160019074Abstract: A method comprising, in a cloud computing system: receiving a new job at the cloud computing system; sampling VMs (Virtual Machines) of the cloud computing system for the load currently handled by each of the VMs; if the load currently handled by the VMs is within operational bounds, sending the new job to one of the VMs which currently handles the highest load compared to other ones of the VMs; and if the load currently handled by the VMs is beyond operational bounds, sending the new job to one of the VMs which currently handles the lowest load compared to other ones of the VMs.Type: ApplicationFiled: July 14, 2015Publication date: January 21, 2016Inventors: Amir Nahir, Ariel Orda, Dan Raz
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Publication number: 20150365092Abstract: A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.Type: ApplicationFiled: June 16, 2014Publication date: December 17, 2015Inventors: Ilia Averbouch, Oded Margalit, Amir Nahir, Yehuda Naveh, Gil Shurek
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Publication number: 20150186251Abstract: Localizing errors by: (i) running a testcase on a hardware processor and saving results; (ii) running the testcase on a software model of the processor and saving results; (iii) recording control flow information during the software run; (iv) determining a set of miscompare data storage locations by comparing the results from the hardware run with those from the software run; (v) based on the set of miscompare data storage locations and/or the control flow information, generating and running a modified version of the testcase that takes a different execution path when run on the software model than did the original testcase when run on the software model; and (vii) comparing the results from the hardware run and the results obtained from the modified software run to provide an indication of similarity between execution paths taken in these respective runs.Type: ApplicationFiled: February 26, 2014Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin
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Publication number: 20150186250Abstract: Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Applicant: International Business Machines CorporationInventors: Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin
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Patent number: 8990622Abstract: Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.Type: GrantFiled: July 29, 2012Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Shimon Landa, Amir Nahir
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Patent number: 8892386Abstract: An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.Type: GrantFiled: July 10, 2011Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Allon Adir, Eyal Bin, Shady Copty, Anatoly Koyfman, Shimon Landa, Amir Nahir, Vitali Sokhin, Elena Tsanko
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Patent number: 8832502Abstract: A method includes executing a first post-silicon testing program by a reference model. During the execution of the first post-silicon testing program, one or more test-cases are generated. The first post-silicon testing program is executed in an offline generation mode. During execution of the first post-silicon testing program each test case is generated in a different memory location. After the execution, generating a second post-silicon testing program that is configured to execute the one or more test-cases. The method further includes executing the second post-silicon testing program on an acceleration platform.Type: GrantFiled: July 25, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Wisam Kadry, Shakti Kapoor, Dimtry Krestyashyn, Shimon Landa, Amir Nahir, John Schumann, Gil Eliezer Shurek, Vitali Sokhin
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Patent number: 8806270Abstract: A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.Type: GrantFiled: November 14, 2011Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Allon Adir, Dimtry Krestyashyn, Charles Meissner, Amir Nahir
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Publication number: 20140032969Abstract: Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.Type: ApplicationFiled: July 29, 2012Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Shimon Landa, Amir Nahir
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Publication number: 20140032966Abstract: A method, apparatus and product for hardware verification using acceleration platform. The method comprising executing a first post-silicon testing program by a reference model, wherein during said executing the first post-silicon testing program one or more test-cases are generated; generating a second post-silicon testing program that is configured to execute the one or more test-cases; and executing the second post-silicon testing program on an acceleration platform.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Manoj Dusanapudi, Wisam Kadry, Shakti Kapoor, Dimtry Krestyashyn, Shimon Landa, Amir Nahir, John Schumann, Gil (Eliezer) Shurek, Vitali Sokhin
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Publication number: 20130124920Abstract: A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations, wherein the plurality of processing entities comprise two or more entities adapted to store values, and one or more entity adapted to load values, wherein each writing entity is associated with a private memory location within a memory unit; storing symbols into an associated target memory location by each of the entities adapted to store values, wherein symbols are stored according to a predetermined order, wherein a symbol is stored using a transaction; loading a multiplicity of private memory locations by the at least one entity adapted to load values, to obtain loaded values; and analyzing the loaded values for at least one invariant.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Allon Adir, Dimtry Krestyashyn, Charles Meissner, Amir Nahir
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Publication number: 20130013246Abstract: An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.Type: ApplicationFiled: July 10, 2011Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Allon Adir, Eyal Bin, Shady Copty, Anatoly Koyfman, Shimon Landa, Amir Nahir, Vitali Sokhin, Elena Tsanko
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Patent number: 8224614Abstract: A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.Type: GrantFiled: October 30, 2009Date of Patent: July 17, 2012Assignee: International Business Machines CorporationInventors: Allon Adir, Maxim Golubev, Andrey Klinger, Amir Nahir
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Publication number: 20110106482Abstract: A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: International Business Machines CorporationInventors: Allon Adir, Maxim Golubev, Andrey Klinger, Amir Nahir
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Patent number: 7530036Abstract: An optimization process is repeatedly invoked over an input, which includes the set of constraints and the objective function. The input of each invocation is randomly modified, so as to cause the optimization process to produce multiple different solutions that satisfy the set of constraints. Multiple random test cases for verifying a compliance of the design with the specifications are generated, based on the multiple different solutions produced by the optimization process.Type: GrantFiled: February 8, 2007Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Amir Nahir, Yossi Shiloach
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Publication number: 20080195982Abstract: A computer-implemented method for verifying a design includes converting test specifications of the design into a set of constraints defined over variables, such that solutions that satisfy the set of constraints define respective valid test cases for verifying the design. An objective function is defined over at least some of the variables. An optimization process is repeatedly invoked over an input, which includes the set of constraints and the objective function. The input of each invocation is randomly modified, so as to cause the optimization process to produce multiple different solutions that satisfy the set of constraints. Multiple random test cases for verifying a compliance of the design with the specifications are generated, based on the multiple different solutions produced by the optimization process.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Inventors: Amir Nahir, Yossi Shiloach