Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.

Abstract: The present disclosure generally relates to an efficient manner of fetching data for write commands. The data can be fetched prior to classification, which is a fetch before mode. The data can alternatively be fetched after classification, which is a fetch after mode. When the data is fetched after classification, the write commands are aggregated until sufficient data associated with any command is split between memory devices. When in fetch before mode, the data should properly align such that data associated with any command is not split between memory devices. Efficiently toggling between the fetch before and fetch after modes will shape how writes are performed without impacting latency and bandwidth without significantly increasing write buffer memory size.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a command is received by the controller from a host device, the controller determines whether the command size is greater than a threshold size. If the command is not greater than the threshold size, the command is sent to a first queue, otherwise, the command is sent to a second queue. Commands are executed from the first queue until a command size tracker value, which increases by a size representative of each command executed from the first queue, equals or exceeds a threshold value. When the command size tracker value equals or exceeds the threshold value, a command from the second queue is executed and the command size tracker value decreases by a size representative of the command from the second queue. Completion messages are sent at specific intervals based on the executing.

Abstract: The present disclosure generally relates to improved fragment processing while command fetching is on-going. Rather than stopping command fetching, the controller uses a short fragment list, while command fetching can continue, to add a fragment. The controller first adds new fragments to the short list with the fragment information. The information is then checked for size. If the fragment information is smaller than the short fragment list, then the fragment list is updated during command fetching. As a command arrives, the controller does a binary search of a sorted fragment list. The results are stored and later scanned by the controller for matches with the short fragment list. If there are no matches in the short list, then the controller uses the stored results to update the search result. If there is a match in the short list then the controller uses the new results to update the search list.

Abstract: The present disclosure generally relate to improved tenant processing by arbitration of commands. Rather than processing a tenant with multiple portions to completion causing increased wait time for preceding tenants, allowing the controller to process commands based on the respective bandwidth allocated to each tenant is beneficial. Through a Weighted Round Robin (WRR) arbiter, the controller is able to allocate a percentage of the bandwidth to each tenant based on the tenant's needs. Once the bandwidth is allocated to the tenants, the controller may then process portions of the commands from the tenants up to the allocated bandwidth per tenant, which avoids the need for commands that are fetched after earlier commands wait for previous commands to complete their processing, but instead process all command portions based on the allocated bandwidth from the WRR arbiter.

Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.

Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.

Abstract: The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a maximum bandwidth of an interface, allocate a portion of the maximum bandwidth to one or more tenants, either: determine a maximum data transfer size (MDTS) setting based on quality of service (QoS) requirements, determine an aggregated queue depth (QD) setting based on QoS requirements, or determine a combined MDTS and aggregated QD setting based on QoS requirements, and provide the determined settings to the one or more tenants.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), specifically utilizing the data storage device memory in the execution of host commands. A controller is configured to receive a command pointer or a data chunk from a host device, mark a destination used for the command pointer or the data chunk, determine whether a last chunk of the command pointer or the data chunk has been received, and determine whether the command pointer or the data chunk uses an illegal combination of locations after determining that the last chunk of the command pointer has been received. The controller is further configured to return an error message to the host device upon determining that the command pointer or the data chunk uses an illegal combination of locations.

Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.

Abstract: The present disclosure generally relates to more effective utilization of write and read bandwidth in submission queues (SQs). The data storage device treats a SQ as two separate SQs: one write SQ and one read SQ. Rather than a single fetch pointer for the entire SQ, the write SQ has a write fetch pointer (WFP) while the read SQ has a separate read fetch pointer (RFP). So long as the individual pointers are less than a queue pointer (QP), the data storage device can still process commands for either read or write SQ even if the other SQ has run out of credits. In so doing, read and write bandwidths can be effectively utilized.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device is DRAM-less. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host device to read data from the memory device, fetch the read data from the memory device, check metadata associated with the read data, determine if the metadata corresponds to the read command, and provide modified read data to the host device when the metadata does not correspond to the read command. The modified read data may be encrypted read data, corrupted read data, or read data that is replaced with debug information. When the host device receives data that is different than the read data that is requested, the modified read data may be unreadable to the host device so that unprivileged access to the read data may be avoided.

Abstract: The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of padding necessary to reach FMU size and also reduces the amount of data to be encrypted. As such, data flushing can be accomplished using the limited amount of remaining power during the power loss event.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.

Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.