Patents by Inventor Amir Segev

Amir Segev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094950
    Abstract: The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV, Judah Gamliel HAHN
  • Patent number: 11934684
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a maximum bandwidth of an interface, allocate a portion of the maximum bandwidth to one or more tenants, either: determine a maximum data transfer size (MDTS) setting based on quality of service (QoS) requirements, determine an aggregated queue depth (QD) setting based on QoS requirements, or determine a combined MDTS and aggregated QD setting based on QoS requirements, and provide the determined settings to the one or more tenants.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11934693
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), specifically utilizing the data storage device memory in the execution of host commands. A controller is configured to receive a command pointer or a data chunk from a host device, mark a destination used for the command pointer or the data chunk, determine whether a last chunk of the command pointer or the data chunk has been received, and determine whether the command pointer or the data chunk uses an illegal combination of locations after determining that the last chunk of the command pointer has been received. The controller is further configured to return an error message to the host device upon determining that the command pointer or the data chunk uses an illegal combination of locations.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11935385
    Abstract: Methods for anomaly detection using dictionary based projection (DBP), and system for implementing such methods. In an embodiment, a method comprises receiving input data including a plurality n of multidimensional data points (MDDPs) with dimension m, applying DBP iteratively to the input data to construct a dictionary D, receiving a newly arrived MDDP (NAMDDP), calculating a score S associated with the NAMDDP as a distance of the NAMDDP from dictionary D, and classifying the NAMDDP as normal or as an anomaly based on score S, wherein classification of the NAMDDP as an anomaly is indicative of detection of an unknown undesirable event.
    Type: Grant
    Filed: July 18, 2021
    Date of Patent: March 19, 2024
    Assignee: ThetaRay Ltd.
    Inventors: Amir Averbuch, Amit Bermanis, David Segev
  • Patent number: 11914900
    Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20240053927
    Abstract: The present disclosure generally relates to more effective utilization of write and read bandwidth in submission queues (SQs). The data storage device treats a SQ as two separate SQs: one write SQ and one read SQ. Rather than a single fetch pointer for the entire SQ, the write SQ has a write fetch pointer (WFP) while the read SQ has a separate read fetch pointer (RFP). So long as the individual pointers are less than a queue pointer (QP), the data storage device can still process commands for either read or write SQ even if the other SQ has run out of credits. In so doing, read and write bandwidths can be effectively utilized.
    Type: Application
    Filed: July 12, 2023
    Publication date: February 15, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 11893248
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host device to read data from the memory device, fetch the read data from the memory device, check metadata associated with the read data, determine if the metadata corresponds to the read command, and provide modified read data to the host device when the metadata does not correspond to the read command. The modified read data may be encrypted read data, corrupted read data, or read data that is replaced with debug information. When the host device receives data that is different than the read data that is requested, the modified read data may be unreadable to the host device so that unprivileged access to the read data may be avoided.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11893275
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device is DRAM-less. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20240028524
    Abstract: The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of padding necessary to reach FMU size and also reduces the amount of data to be encrypted. As such, data flushing can be accomplished using the limited amount of remaining power during the power loss event.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 11853218
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Amir Rozen, Shay Benisty
  • Patent number: 11847323
    Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: December 19, 2023
    Assignee: Westem Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20230393772
    Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Shay Benisty, Amir Rozen, Amir Segev
  • Publication number: 20230393738
    Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20230384976
    Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20230376244
    Abstract: The present disclosure generally relates to an efficient manner of fetching data for write commands. The data can be fetched prior to classification, which is a fetch before mode. The data can alternatively be fetched after classification, which is a fetch after mode. When the data is fetched after classification, the write commands are aggregated until sufficient data associated with any command is split between memory devices. When in fetch before mode, the data should properly align such that data associated with any command is not split between memory devices. Efficiently toggling between the fetch before and fetch after modes will shape how writes are performed without impacting latency and bandwidth without significantly increasing write buffer memory size.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 11809742
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20230328308
    Abstract: A computerized content synchronization system is configured to perform the following method: (a) obtain information indicative of multiple content streams, associated with a shared content; (b) provide algorithms, each algorithm configured to perform at least one of: identify, within the information, synchronization point(s) between the streams; calculate a timeline difference between the streams; and (c) responsive to a determination that the system does not possess, external to the information indicative of the streams, information concerning characteristics of a content pipeline architecture of each stream, which is capable of relating timelines of streams, perform the following: (i) choose an algorithm, based on defined criterion parameter(s) associated with algorithm characteristics, and on an analysis of the information; and (ii) run the chosen algorithm. This facilitates a synchronized consumption of the content by consumer(s), The consumer(s) is configured to consume the multiple content streams.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Inventors: Matan MARCIANO, Gil Shimon LUBLINER, Eyal GENIS, Andrew YOUNAN, Guy ZISMAN, Gad GEFFEN, Amir SHIMONI, Amir SEGEV
  • Patent number: 11768606
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a plurality of fetch requests, determine a first number of requests, second number of requests, and a third number of requests of the plurality of fetch requests, and balance an execution of the first number of requests, the second number of requests, and the third number of requests so that a first ratio of the data requests to the PRP requests and a second ratio of the data requests to the HMB requests is about 1. The plurality of fetch requests includes PRP requests, HMB requests, and data requests. The first number of requests corresponds to a number of the PRP requests. The second number of requests corresponds to a number of the HMB requests. The third number of requests corresponds to a number of the data requests.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: September 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20230290329
    Abstract: An acoustic signal cancellation system is configured to perform: (a) provide a user device, associated with the system, and an audio capture device. (b) receive at system a captured signal indicative of a captured acoustic signal. It's received at capture device, and comprises a second acoustic signal generated by a second device, external to user device. (c) receive, from external source, a reference signal, indicative of a content included in the second signal. (d) in a case that a content of reference signal and the content in second signal are not time-synchronized, generate a synchronized reference signal, based on reference signal. Content of synchronized reference signal and second signal content are time-synchronized. (e) perform acoustic signal cancelling of that portion of captured signal which corresponds to second signal, based on reference signal. Generate reduced signal. This facilitates output of reduced signal to third device.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Inventors: Eder ROBINS, Igor LVOVSKY, Shay EFRATI, Guy ZISMAN, Andrew YOUNAN, Gad GEFFEN, Amir SHIMONI, Amir SEGEV
  • Publication number: 20230289226
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a shutdown notification, fetch one or more command identifiers from a submission queue of a host device, generate error indications for the one or more command identifiers, and send a completion message, including the generated error indication, for each of the one or more command identifiers to the host device. The controller is further configured to push non-processed pending commands to a completion finite state machine, where the controller generates an error indication for each of the non-processed pending commands and sends a completion message, including the generated error indication, for each of the non-processed pending commands to the host device. While the controller is fetching command identifiers and pushing non-process commands, the controller is configured to continue processing processed commands in parallel.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY