Abstract: Gap processing is utilized to reorder out-of-order submissions on the normal submission queue. The controller is able to process logical block addresses (LBAs) that are received through the use of a normal NVMe submission queue (SQ) and a private SQ. The normal NVMe SQ will store the LBAs of commands that may arrive out of sequential order for processing. The private SQ is used to store an LBA that is received after a gap is detected. The private SQ is only read after a command is received on the normal SQ that contains the current First Gap LBA. If no entry in the private SQ is sequentially after the first gap LBA, no processing of the private SQ occurs. If the pulled LBA is next, then the LBA will be processed by the data storage device. If the pulled LBA is not next, then the zone gap processing will send the LBA back to the private SQ.

Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.

Abstract: Instead of handling transaction layer packets (TLP) without over-read usage, utilize adaptive over-read. As TLPs are transferred from the host along the Peripheral Component Interconnect express (PCIe) in the fabric to the device, some performance options are best suited. The fabric prefers bytes read in multiples of 64 bytes, while the PCIe works best in smaller byte chunks. Adaptive over-read allows a device to periodically check a system through testing over-read usage to compare the results for best performance of the system. The system is checked periodically, because different devices in the system can have an effect on the fabric and PCIe that may change performance preferences.

Abstract: Instead of allocating unused resources, offload work from the host, and move to just-in-time, low capacity DRAM memory allocation. The host does a read and receives the location of the data in the response. This will offload the host from managing physical region page (PRP) lists and reduce time randomly allocated to memory allowing the memory to remain empty. The DRAM savings is in the low memory foot print. The data storage device counts the number of bytes that have been read by the host (per flash memory unit (FMU)), and the data storage device can release the buffer as soon as all the data has been read. The buffers are managed more efficiently as the data storage device knows automatically when a buffer should be allocated/de-allocated just-in-time. This provides a short timespan for the data, reducing the amount of DRAM utilized.

Abstract: There is a tradeoff between the amount of power consumption decreased and the latency needed to return a data storage device back to an operational power mode. When the data storage device receives a wake up indication from a host device, a controller of the data storage device initiates a counter in order to determine a host exit latency. Based on the host exit latency, the controller determines a group of low power state entrance actions from a plurality of groups to perform during a next entrance into a firmware active idle state based on an associated completion wake up time and the host exit latency. The controller selects the group whose completion wake up time is closest to the host exit latency and less than or equal to the host exit latency. The controller performs the selected groups low power state entrance actions during a next entrance into the firmware active idle state.

Abstract: Instead of using programmable block size aggregation, a lower multiple of page, and down to a page size aggregation is used. A bad block prediction unit in a controller is able to predict when a programmable block has a bad page. The bad block prediction unit can lower the aggregation size of a programmable block by monitoring the life cycle of the programmable block through bad block statistic collection. When the accumulation size passes a threshold, the bad block prediction unit lowers the aggregation size. The bad block prediction unit can also predict when to lower aggregation size based on the number of reconstructions. An aggregate size level is set at a page boundary, and once the number of reconstructions reaches that page boundary, the bad block prediction unit lowers the aggregation size to page aggregation. The bad block prediction unit is able to predict both life cycle threshold changes and reconstructions changes.

Abstract: The present disclosure generally relates to more effective utilization of write and read bandwidth in submission queues (SQs). The data storage device treats a SQ as two separate SQs: one write SQ and one read SQ. Rather than a single fetch pointer for the entire SQ, the write SQ has a write fetch pointer (WFP) while the read SQ has a separate read fetch pointer (RFP). So long as the individual pointers are less than a queue pointer (QP), the data storage device can still process commands for either read or write SQ even if the other SQ has run out of credits. In so doing, read and write bandwidths can be effectively utilized.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a shutdown notification, fetch one or more command identifiers from a submission queue of a host device, generate error indications for the one or more command identifiers, and send a completion message, including the generated error indication, for each of the one or more command identifiers to the host device. The controller is further configured to push non-processed pending commands to a completion finite state machine, where the controller generates an error indication for each of the non-processed pending commands and sends a completion message, including the generated error indication, for each of the non-processed pending commands to the host device. While the controller is fetching command identifiers and pushing non-process commands, the controller is configured to continue processing processed commands in parallel.

Abstract: Instead of having uncertainty when waiting on completions, utilize unordered input output memory write (UIOMWr) to ensure the completions of the write. Using UIOMWr, the data storage device will write the competitions to a host dynamic random access memory (DRAM). When the device receives an approval of the completion, the device knows that the write to the host DRAM was successful. The approval will trigger the device to have the message signaled interrupts extended (MSIx) send an interrupt request (IRQ) to the host. The IRQ will pass through the PCIe and will be received by the host CPU. The host CPU will then process any pending completions in the host DRAM. An MSIx tag can be added to the completion (at the UIOMWr TLP level) that is assigned to multiple submission queues (SQ). When the MSIx tag is received by the host and device, the host and device will know what information needs to be pulled to avoid the need for translation later on.

Abstract: In order to ensure that a bandwidth allocated to each tenant of a plurality of tenants of a data storage device is maintained, a controller of the data storage device may split a large read command, received from a host device, into a plurality of chunks, where each chunk corresponds to a distinct portion of the split large read command. Because the allocated bandwidth for a tenant is static, one or more chunks of the plurality of chunks, up to the allocated bandwidth, are executed, such that the bandwidth required to perform the one or more chunks does not exceed the allocated bandwidth for the particular tenant. Split information is added to the plurality of chunks in order to maintain coherency when executing the one or more chunks. Therefore, the agreed-upon allocated bandwidth for each tenant is maintained while performing large read commands requiring more bandwidth than allocated.

Abstract: Instead of an arbitration over the link not considering bursts, a smart scheduler in a solid state drive (SSD) host interface is burst aware. The scheduler considers the type of transactions that are going to be sent over the interface. The scheduler sends the transactions in the most efficient way while maximizing the efficiency over the host DRAM. The schedulers may be calibrated from time to time on-the-fly to find the optimal configurations adapted to the current workload. The scheduler will organize the packets selected by the arbitration module so that the data transfers are sent in a burst of a predetermined sized to the host for optimum performance. For further optimization other packet types are sent in bursts as well.

Abstract: Instead of maximizing the possible bandwidth of device, utilize time slice credits (TSC), to ensure bandwidth average over a sliding window. When the average is ensured over a sliding window, the device should not care when the host decides to sample a 100 mSec for example, as the average will always be correct. By utilizing set percentage of predetermined allotment for the average bandwidth requirement, the system can give out credit on a predetermined interval. The credit is given out based on usage and once credit is depleted, data cannot be sent until more credit is accumulated. When data is not sent, the system is given a chance to accumulate credit to increase the amount of data sent. Once credit is at a level high enough to send data the device will send the data, but not at a speed that will surpass the average bandwidth requirement.

Abstract: Instead of the firmware (FW) monitoring for both an overlap read command and a write protected (WP) overlapped write command, the FW can monitor the overlap table only. The controller will receive a read command or an overlap read command. If the command is not an overlap read command, then the controller will process the command normally. If the command is an overlap read command, then the controller will look for the write command that is being overlapped. When passing the write overlap of write protect (WP) into the data path instead of the exception queue, the FW is limited to monitoring the overlap table. As such, when the WP command is completed the entry is removed by the data path. As a result, the FW can limit monitoring to when the data path clears the overlap table.

Abstract: Instead of handing gaming/streaming operations and I/O operations using the same error correction code (ECC) scheme, use a different ECC scheme for different cases. When for gaming/streaming user data cases, ECC is not required, and the protection information (PI) provided by the host is used instead. If the host does not provide the PI for the specific command for gaming/streaming user data, the logic generates and injects ECC transparently to the rest of the logic. For I/O operations the standard ECC scheme will be used, which will include adding cyclic redundancy check (CRC) to the data. Once the CRC is added to the data, the data and the CRC will be encrypted. After a header is added to the data and the CRC all of the information is protected with flash memory unit (FMU) CRC (FMU-CRC).

Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of padding necessary to reach FMU size and also reduces the amount of data to be encrypted. As such, data flushing can be accomplished using the limited amount of remaining power during the power loss event.

Abstract: Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion for a host. The controller will then return to the key index table to count the completed commands and send the completion to the host.

Abstract: A data storage device implements a Zoned Namespace (ZNS) storage architecture. The data storage device delays the execution of write commands that are received out of sequence instead of rejecting the write commands. The write commands that are received out of sequence are reordered according to a logical block address (LBA) associated with each write command. The data storage device also checks for deadlock conditions that may arise due to the execution of the write commands being delayed and/or due to the write commands being reordered.

Abstract: Instead of handling resources with one generic method, the controller can use a static method or dynamic method to handle the resources. The controller communicates to the host as to the number of resources the controller has for keeping doorbell times. The controller will also communicate with the host how those resources are used. The static method focuses on creating dedicated submission queues (SQ), while the dynamic method provides a hint during the doorbell execution. The static method further focuses on improving priority, while the dynamic method focuses on canceling commands that have timed out. The static method and the dynamic method can be combined to further support the hosts requirements.