Patents by Inventor Amir Segev

Amir Segev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12182451
    Abstract: The present disclosure generally relates to improved fragment processing while command fetching is on-going. Rather than stopping command fetching, the controller uses a short fragment list, while command fetching can continue, to add a fragment. The controller first adds new fragments to the short list with the fragment information. The information is then checked for size. If the fragment information is smaller than the short fragment list, then the fragment list is updated during command fetching. As a command arrives, the controller does a binary search of a sorted fragment list. The results are stored and later scanned by the controller for matches with the short fragment list. If there are no matches in the short list, then the controller uses the stored results to update the search result. If there is a match in the short list then the controller uses the new results to update the search list.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: December 31, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 12175114
    Abstract: Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: December 24, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Amir Segev, Judah Gamliel Hahn
  • Publication number: 20240402927
    Abstract: In order to ensure that a bandwidth allocated to each tenant of a plurality of tenants of a data storage device is maintained, a controller of the data storage device may split a large read command, received from a host device, into a plurality of chunks, where each chunk corresponds to a distinct portion of the split large read command. Because the allocated bandwidth for a tenant is static, one or more chunks of the plurality of chunks, up to the allocated bandwidth, are executed, such that the bandwidth required to perform the one or more chunks does not exceed the allocated bandwidth for the particular tenant. Split information is added to the plurality of chunks in order to maintain coherency when executing the one or more chunks. Therefore, the agreed-upon allocated bandwidth for each tenant is maintained while performing large read commands requiring more bandwidth than allocated.
    Type: Application
    Filed: July 6, 2023
    Publication date: December 5, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Elkana RICHTER, Shay BENISTY, Amir SEGEV
  • Publication number: 20240378151
    Abstract: A data storage device implements a Zoned Namespace (ZNS) storage architecture. The data storage device delays the execution of write commands that are received out of sequence instead of rejecting the write commands. The write commands that are received out of sequence are reordered according to a logical block address (LBA) associated with each write command. The data storage device also checks for deadlock conditions that may arise due to the execution of the write commands being delayed and/or due to the write commands being reordered.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 14, 2024
    Inventors: Rotem Sela, Amir Segev
  • Publication number: 20240370210
    Abstract: Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion for a host. The controller will then return to the key index table to count the completed commands and send the completion to the host.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 7, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20240319779
    Abstract: There is a tradeoff between the amount of power consumption decreased and the latency needed to return a data storage device back to an operational power mode. When the data storage device receives a wake up indication from a host device, a controller of the data storage device initiates a counter in order to determine a host exit latency. Based on the host exit latency, the controller determines a group of low power state entrance actions from a plurality of groups to perform during a next entrance into a firmware active idle state based on an associated completion wake up time and the host exit latency. The controller selects the group whose completion wake up time is closest to the host exit latency and less than or equal to the host exit latency. The controller performs the selected groups low power state entrance actions during a next entrance into the firmware active idle state.
    Type: Application
    Filed: July 6, 2023
    Publication date: September 26, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nissim ELMALEH, Amir SEGEV, Shay BENISTY
  • Publication number: 20240256124
    Abstract: The present disclosure generally relates improved key-per IO (KIPO) processing for multiple tenants. Rather than when a tenant requests a key change to stop tenants from working, indirect-double-indexing can be used to prevent bandwidth loss in tenants during adaptions for other tenants. When a tenant requests to manipulate the key-index table, the system will keep working. The current key index list will be duplicated. While the duplicated key-index list is manipulated according to the request, all tenants may still work on their current key-index tables until the request is complete. Once the request is complete, the tenant with the request will switch to the new table, while the old table is updated. Once the old table is updated, the tenant will switch to the updated table for continued work. No tenant, including the tenant that makes the request, continues working as the request is completed.
    Type: Application
    Filed: July 19, 2023
    Publication date: August 1, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 12045501
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: July 23, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Shay Benisty, Amir Segev
  • Patent number: 12039198
    Abstract: The present disclosure generally relates to an efficient manner of fetching data for write commands. The data can be fetched prior to classification, which is a fetch before mode. The data can alternatively be fetched after classification, which is a fetch after mode. When the data is fetched after classification, the write commands are aggregated until sufficient data associated with any command is split between memory devices. When in fetch before mode, the data should properly align such that data associated with any command is not split between memory devices. Efficiently toggling between the fetch before and fetch after modes will shape how writes are performed without impacting latency and bandwidth without significantly increasing write buffer memory size.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: July 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Publication number: 20240201847
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a command is received by the controller from a host device, the controller determines whether the command size is greater than a threshold size. If the command is not greater than the threshold size, the command is sent to a first queue, otherwise, the command is sent to a second queue. Commands are executed from the first queue until a command size tracker value, which increases by a size representative of each command executed from the first queue, equals or exceeds a threshold value. When the command size tracker value equals or exceeds the threshold value, a command from the second queue is executed and the command size tracker value decreases by a size representative of the command from the second queue. Completion messages are sent at specific intervals based on the executing.
    Type: Application
    Filed: July 6, 2023
    Publication date: June 20, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Elkana RICHTER, Shay BENISTY, Amir SEGEV
  • Publication number: 20240192889
    Abstract: The present disclosure generally relates to improved fragment processing while command fetching is on-going. Rather than stopping command fetching, the controller uses a short fragment list, while command fetching can continue, to add a fragment. The controller first adds new fragments to the short list with the fragment information. The information is then checked for size. If the fragment information is smaller than the short fragment list, then the fragment list is updated during command fetching. As a command arrives, the controller does a binary search of a sorted fragment list. The results are stored and later scanned by the controller for matches with the short fragment list. If there are no matches in the short list, then the controller uses the stored results to update the search result. If there is a match in the short list then the controller uses the new results to update the search list.
    Type: Application
    Filed: July 19, 2023
    Publication date: June 13, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20240168801
    Abstract: The present disclosure generally relate to improved tenant processing by arbitration of commands. Rather than processing a tenant with multiple portions to completion causing increased wait time for preceding tenants, allowing the controller to process commands based on the respective bandwidth allocated to each tenant is beneficial. Through a Weighted Round Robin (WRR) arbiter, the controller is able to allocate a percentage of the bandwidth to each tenant based on the tenant's needs. Once the bandwidth is allocated to the tenants, the controller may then process portions of the commands from the tenants up to the allocated bandwidth per tenant, which avoids the need for commands that are fetched after earlier commands wait for previous commands to complete their processing, but instead process all command portions based on the allocated bandwidth from the WRR arbiter.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 11983428
    Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: May 14, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Amir Rozen, Amir Segev
  • Publication number: 20240152293
    Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 9, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20240143228
    Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY, Rotem SELA
  • Publication number: 20240143508
    Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV
  • Publication number: 20240094950
    Abstract: The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV, Judah Gamliel HAHN
  • Patent number: 11934684
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a maximum bandwidth of an interface, allocate a portion of the maximum bandwidth to one or more tenants, either: determine a maximum data transfer size (MDTS) setting based on quality of service (QoS) requirements, determine an aggregated queue depth (QD) setting based on QoS requirements, or determine a combined MDTS and aggregated QD setting based on QoS requirements, and provide the determined settings to the one or more tenants.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11934693
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), specifically utilizing the data storage device memory in the execution of host commands. A controller is configured to receive a command pointer or a data chunk from a host device, mark a destination used for the command pointer or the data chunk, determine whether a last chunk of the command pointer or the data chunk has been received, and determine whether the command pointer or the data chunk uses an illegal combination of locations after determining that the last chunk of the command pointer has been received. The controller is further configured to return an error message to the host device upon determining that the command pointer or the data chunk uses an illegal combination of locations.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11914900
    Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty