Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create one or more thresholds for sending sideband information to a host device, determine that a link state is in a state other than L0, retain sideband information until the one or more thresholds is reached, and send the sideband information to the host device upon reaching the one or more thresholds for a corresponding link state. The one or more thresholds correspond to a link state between the host device and the data storage device. The thresholds are either based on an amount of sideband information retained, a time of retaining sideband information, or a combination of the amount of sideband information retained and the time of retaining sideband information. The sideband information is retained and sent in a first-in first-out order.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device is DRAM-less. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.

Abstract: Aspects of a storage device are provided that allow a controller to leverage cache to minimize occurrence of HMB address overlaps between different HMB requests. The storage device may include a cache and a controller coupled to the cache. The controller may store in the cache, in response to a HMB read request, first data from a HMB at a first HMB address. The controller may also store in the cache, in response to an HMB write request, second data from the HMB at a second HMB address. The controller may refrain from processing subsequent HMB requests in response to an overlap of the first HMB address with an address range including the second HMB address, and the controller may resume processing the subsequent HMB requests after the first data is stored. As a result, turnaround time delays for HMB requests may be reduced and performance may be improved.

Abstract: The present disclosure generally relates to searching an overlap table for data requested to be read in a plurality of read commands received. Rather than searching the table for data corresponding to each command individually, the searching occurs for the plurality of commands in parallel. Furthermore, the overlap table can comprise multiple data entries for each line. The number of read commands can be accumulated prior to searching, with the accumulating being a function of a queue depth permitted by the host device. Parallel searching of the overlap table reduces the average search time.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using Universal Flash Storage (UFS) interface protocols, provide a hint to the host device, switch between a first mode and a second mode, retrieve the data from the memory device, and deliver the data to the host device. The hint includes an indication of what order data will be received from the data storage device. The order of the data will be in a different order than a requested order after providing the hint.

Abstract: A storage system and method for command execution ordering by security key are provided. In one example, the storage system has a non-volatile memory, a volatile memory storing a plurality of keys, and a controller with a cache storing a subset of the plurality of keys. The storage system gives priority to a command whose key is stored in the cache in the controller over commands whose keys are stored only in the volatile memory. This avoids transferring a key from the volatile memory to the cache in the controller, thereby improving efficiency of the storage system.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a parent physical function (PF), receive one or more child PFs, determine whether any part of a first child command of a first child PF of the one or more child PFs can be executed prior to receiving approval from the parent PF, and start executing the first child command. The controller is further configured to initialize an indirect queue, set fetching pointers of the indirect queue to the first child command, mimic a doorbell for the first child command, fetch the first child command, determine whether the first child command has started execution by a child PF flow, and complete the first child command.

Abstract: The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.

Abstract: Systems and methods, according to the present disclosure, determines a duration of the current queue of commands in the controller, executes all full commands capable of being executed prior to the beginning of a low power cycle. Commands that are not executed may be re-fetched when the device enters a power mode. In an alternate embodiment, a portion of a command that is executable prior to the beginning of a low power cycle is executed, with the un-executed portion of the command being stored on the device, in an “always on” or AON memory. This un-executed portion is fetched and executed when the device enters the power mode.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a parent physical function (PF), receive one or more child PFs, determine whether any part of a first child command of a first child PF of the one or more child PFs can be executed prior to receiving approval from the parent PF, and start executing the first child command. The controller is further configured to initialize an indirect queue, set fetching pointers of the indirect queue to the first child command, mimic a doorbell for the first child command, fetch the first child command, determine whether the first child command has started execution by a child PF flow, and complete the first child command.

Abstract: The controller is configured to receive commands from a host device through a PCIe bus having a MAC, send data to the host device through the PCIe bus, and execute a function level reset (FLR) command. The controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. The units are configured to prevent transactions associated with the FLR command to pass from the DMA to the MAC during execution of the FLR command, where the preventing transactions comprises receiving a request from the DMA, storing the request in a pipe, removing the request from the pipe, and providing a response to the DMA without delivering the request to the MAC. The drain and drop unit is configured to drop a MAC generated response.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to set a decoder in data mode, read host memory buffer data and hashes from a host memory buffer, generate a first calculated hash, set the decoder in hash mode, generate a second calculated hash, and determine whether the second calculated hash is the same as a root hash. The controller is further configured to set an encoder in data mode, generate a first new hash, write new data and the first new hash to a host memory buffer, set the encoder to hash mode, calculate a second new hash, and update a root hash with the second new hash.

Abstract: The present disclosure generally relates to efficient transfer layer packet (TLP) fragmentation in a data storage device. For an unaligned read from host flow, an amount of data sufficient to be aligned is transferred to the memory device from the host while the remainder of the data is stored in cache of the data storage device to be delivered to memory device at a later time. For an unaligned write to host flow, the unaligned data is written to cache and at a later time the cache will be flushed to the host device. In both cases, while the total data would be unaligned, a portion of the data is placed in cache so that the data not placed in cache is aligned. The data in cache is delivered at a later point in time.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to set a decoder in data mode, read host memory buffer data and hashes from a host memory buffer, generate a first calculated hash, set the decoder in hash mode, generate a second calculated hash, and determine whether the second calculated hash is the same as a root hash. The controller is further configured to set an encoder in data mode, generate a first new hash, write new data and the first new hash to a host memory buffer, set the encoder to hash mode, calculate a second new hash, and update a root hash with the second new hash.

Abstract: A computerized method that may include (i) receiving, by one or more slicers, multiple input streams, the multiple input streams comprise (a) an input video stream that comprises visual information obtained from an event, and (b) at least one additional stream related to the event; (ii) converting the multiple input streams to a group of EISCVSs, different input streams are mapped to different EISCVSs; (iii) determining, by one or more personalization entities, a content to be sent to one or more user devices; (iv) generating, by the one or more personalization entities and based on the determining, the at least one personalized content stream to be sent to one or more user devices; and (v) sending the at least one personalized content stream to the one or more user devices.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive new debug information, determine that a debug buffer does not have any available free entries for the new debug information, compare the priority information to a lowest priority information of old debug information stored in the debug buffer, remove a most recent old debug information that has a lowest priority information from the debug buffer, and place the new debug information and corresponding priority information in the debug buffer.

Abstract: A computerized method for transmitting one or more video streams, the method may include receiving at least one input video stream that comprises visual information obtained from multiple fields of view that differ from each other; converting the at least one input video stream to a group of encoded independent self-contained video streams (EISCVSs), by performing a codec-agnostic process; wherein different EISCVSs comprise visual information from different spatial segments of the at least one input video stream; receiving a first request to receive video information related to a first direction related to a first user; generating a first video stream that comprises a first sub-set of EISCVSs that is related to the first direction; and sending the first video stream to a device of the first user, over a first communication link that has a first bandwidth that is lower than a bandwidth required to convey the input video stream.

Abstract: A data storage device and method for securely storing and retrieving data at a data storage device. The disclosure includes a reverse encryption where a decryption function is applied to plaintext data to generate ciphertext data. Conversely, the disclosure includes applying an encryption function to ciphertext data to generate plaintext data. This involves using an encryption function that is inverse, and symmetric, to the decryption function. In some specific examples, this includes sharing cryptography engines for securing user data in a storage medium and securing device management data in host memory.

Abstract: A circuit debug apparatus for debugging an integrated circuit that causes a functional fault may include a processor configured to extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode. The scan pattern includes a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit. The processor may also be configured to apply a modified scan pattern to the integrated circuit while the integrated circuit is in the scan mode, where the modified scan pattern includes a test pattern configured to eliminate the functional fault. The processor may be further configured to determine whether the integrated circuit with the modified scan pattern produces the functional fault while the integrated circuit is in a functional mode.