Abstract: An example system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including: determining that a write request references a partially aligned translation unit; identifying a first entry in a translation map, such that the first entry identifies a first physical block of the memory device, such that the first physical block is mapped to the partially aligned translation unit; creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit; linking, in the translation map, the first entry and the second entry; and writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.

Abstract: A reset counter associated with a zone of the memory device is maintained. The reset counter represents a number of times the zone has been reset. In response to receiving a write command directed to the zone of the memory device, a target portion of the zone that is not open is identified. A first portion from a free portion list is identified. The program erase count of the first portion corresponds to the reset counter associated with the zone. The first portion is allocated to the zone.

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.

Abstract: A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

Abstract: An error associated with host data written to a page of a storage area of a memory sub-system is detected. A determination is made that parity data corresponding to the host data is stored in a cache memory of the memory sub-system. A data recovery operation is performed based on the parity data stored in the cache memory.

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

Abstract: A command to migrate data from a source address to a destination address is detected. One or more parameters associated with the source address are provided as input to a trained machine learning model. A read verify relevance if received as output from the trained machine learning model. Responsive to determining that the read verify relevance satisfies a condition, the command is performed to migrate the data.

Abstract: A method includes issuing a program command to a logic unit (LUN) of a memory device, writing a plurality of commands to a transfer queue within the memory device, detecting a program failure for the LUN of the memory device, and maintaining a number of the plurality of commands in the transfer queue.

Abstract: An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

Abstract: An error associated with host data written to a page of a storage area of a memory sub-system is detected. A determination is made that parity data corresponding to the host data is stored in a cache memory of the memory sub-system. A data recovery operation is performed based on the parity data stored in the cache memory.

Abstract: A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

Abstract: A system includes: a memory device; and a processing device, operatively coupled with the memory device, to perform operations including: dividing a translation map into a plurality of portions of the translation map, the translation map mapping a plurality of logical block addresses to a plurality of physical block addresses of the memory device, each of the plurality of portions of the translation map corresponding to a plurality of blocks of the memory device, wherein a portion of the plurality of portions of the translation map comprises a plurality of entries, each entry mapping a logical block address to a physical block address of the memory device; updating, responsive to receiving a data access request, a counter of data access operations performed using each of the plurality of portions of the translation map; responsive to determining that a predefined condition is satisfied, identifying a portion of the plurality of portions of the translation map based on the counter of data access operations; id

Abstract: Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

Abstract: A number of data access operations is tracked where the data access operations are associated with each of a plurality of portions of a translation map. The translation map maps a plurality of logical block addresses to a plurality of physical block addresses of the memory device. A criterion to perform a garbage collection operation is determined to be satisfied. The garbage collection operation is to be performed on a block of the memory component. The block for performing the garbage collection operation is identified based on the number of data access operations associated with each of the plurality of portions of the translation map. The garbage collection operation is performed on the identified block.

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

Abstract: An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.