Patents by Inventor Amit Bleiweiss
Amit Bleiweiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11544461Abstract: The disclosure provides a natural language processing (NLP) model arranged to operate on two lexicons, where one lexicon is a sub-set of the other lexicon. The NLP model can be arranged to generate output based on the sub-set lexicon and exit processing of the NLP model, to potentially save computation cycles.Type: GrantFiled: May 14, 2019Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Barak Battach, Amit Bleiweiss, Haim Barad
-
Patent number: 11526736Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to map workloads. An example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.Type: GrantFiled: August 15, 2019Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Estelle Aflalo, Amit Bleiweiss, Mattias Marder, Eliran Zimmerman
-
Publication number: 20220261357Abstract: Systems, apparatuses, and methods include technology that determines, with a neural network, that a first eviction node stored in a cache will be evicted from the cache based on a cache policy. The first eviction node is part of a plurality of nodes associated with a graph. Further, a subset of nodes of the plurality of nodes remains in the cache after the eviction of the first eviction node from the cache. The technology further tracks a number of cache hits on the cache during an aggregation operation associated with a hardware accelerator, where the aggregation operation is executed on the subset of nodes that remain in the cache after the eviction of the eviction node from the cache. The technology executes a training process on the neural network to adjust the cache policy based on the number of the cache hits.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Ronen Gabbai, Amit Bleiweiss, Ohad Falik, Amit Gur, Almog Tzabary
-
Publication number: 20220237850Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 10, 2022Publication date: July 28, 2022Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 11373088Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.Type: GrantFiled: December 30, 2017Date of Patent: June 28, 2022Assignee: INTEL CORPORATIONInventors: Amit Bleiweiss, Anavai Ramesh, Asit Mishra, Deborah Marr, Jeffrey Cook, Srinivas Sridharan, Eriko Nurvitadhi, Elmoustapha Ould-Ahmed-Vall, Dheevatsa Mudigere, Mohammad Ashraf Bhuiyan, Md Faijul Amin, Wei Wang, Dhawal Srivastava, Niharika Maheshwari
-
Publication number: 20220139101Abstract: An activity recording system is provided. The activity recording system includes a three-dimensional camera, a sensor arrangement that is fitted to a subject being recorded, and an activity recording device. The activity recording device receives image information from the three-dimensional camera and sensor arrangement information from the sensor arrangement. Both the image information and the sensor arrangement information include location measurements. The sensor arrangement information is generated by location sensors that are positioned at target features of the subject to be tracked. The sensor arrangement information is a key to the image information that specifies where, in any given image, the target features of the subject lie. Activity data having these characteristics may be applied to solve a variety of system development problems. Such activity data can be used to training machine learning components or test computer vision components for a fraction of the cost of using conventional techniques.Type: ApplicationFiled: September 13, 2021Publication date: May 5, 2022Inventor: Amit Bleiweiss
-
Publication number: 20220076118Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 17, 2021Publication date: March 10, 2022Applicant: Intel CorporationInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amitai Armon, Uzi Sarel
-
Publication number: 20220067496Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 10, 2021Publication date: March 3, 2022Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
-
Publication number: 20220058469Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: ApplicationFiled: August 5, 2021Publication date: February 24, 2022Applicant: Intel CorporationInventors: TOMER SCHWARTZ, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
-
Patent number: 11250610Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 28, 2020Date of Patent: February 15, 2022Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 11238338Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: February 1, 2022Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amital Armon, Uzi Sarel
-
Patent number: 11138421Abstract: An activity recording system is provided. The activity recording system includes a three-dimensional camera, a sensor arrangement that is fitted to a subject being recorded, and an activity recording device. The activity recording device receives image information from the three-dimensional camera and sensor arrangement information from the sensor arrangement. Both the image information and the sensor arrangement information include location measurements. The sensor arrangement information is generated by location sensors that are positioned at target features of the subject to be tracked. The sensor arrangement information is a key to the image information that specifies where, in any given image, the target features of the subject lie. Activity data having these characteristics may be applied to solve a variety of system development problems. Such activity data can be used to training machine learning components or test computer vision components for a fraction of the cost of using conventional techniques.Type: GrantFiled: January 30, 2020Date of Patent: October 5, 2021Assignee: Intel CorporationInventor: Amit Bleiweiss
-
Patent number: 11132601Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: September 28, 2021Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
-
Patent number: 11100393Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: August 24, 2021Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
-
Publication number: 20210256272Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Applicant: Intel CorporationInventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
-
Patent number: 11093822Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: August 17, 2021Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
-
Patent number: 11087206Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: GrantFiled: April 28, 2017Date of Patent: August 10, 2021Assignee: INTEL CORPORATIONInventors: Tomer Schwartz, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
-
Patent number: 11079825Abstract: Apparatus, devices, systems, methods, and articles of manufacture are disclosed to allocate power in a computing device. An example system includes a compiler to: analyze power consumption behavior of power consumption units of the computing device; build a power profile; and generate source code with hints of the power profile. The example system includes a power control circuit to: develop a power policy using the hints of the power profile and requests for power licenses from the power consumption units of the computing device; and allocate power to the power consumption units based on the power profile.Type: GrantFiled: August 13, 2019Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Anat Heilper, Eran Dagan, Amit Bleiweiss, Amit Gur
-
Patent number: 11048333Abstract: A system and method for close range object tracking are described. Close range depth images of a user's hands and fingers or other objects are acquired using a depth sensor. Using depth image data obtained from the depth sensor, movements of the user's hands and fingers or other objects are identified and tracked, thus permitting the user to interact with an object displayed on a screen, by using the positions and movements of his hands and fingers or other objects.Type: GrantFiled: March 6, 2018Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Gershom Kutliroff, Yaron Yanai, Amit Bleiweiss, Shahar Fleishman, Yotam Livny, Jonathan Epstein
-
Publication number: 20210141604Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 24, 2020Publication date: May 13, 2021Applicant: Intel CorporationInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby