Patents by Inventor Amit Chandra

Amit Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8332798
    Abstract: In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Apple Inc.
    Inventors: Amit Chandra, Muthukumaravelu Velayoudame
  • Patent number: 8332699
    Abstract: In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: December 11, 2012
    Assignee: Apple Inc.
    Inventors: Amit Chandra, Muthukumaravelu Velayoudame, Mandeep Singh, Michael Mar
  • Publication number: 20120303395
    Abstract: Systems and methods of evaluating and/or assessing the health of a relationship are provided. In some examples, the systems and methods may include identifying a first party and a second party in a relationship. The systems and methods may further include determining a plurality of parameters for evaluation. In some examples, a first portion of the parameters may be evaluated based on what the second party thinks of the first party from a business engagement perspective. Another portion of the parameters may be evaluated based on how well prepared the first party is to meet the business needs of the second party. The scores may be combined to determine an overall health of the relationship and, in some examples, the results may be represented graphically and/or using color to indicate the health of the relationship.
    Type: Application
    Filed: May 23, 2011
    Publication date: November 29, 2012
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Ankit Saxena, Viral Chhaya, Amit Chandra
  • Publication number: 20120233577
    Abstract: In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 13, 2012
    Inventors: Amit Chandra, Muthukumaravelu Velayoudame
  • Publication number: 20110296264
    Abstract: In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Inventors: Amit Chandra, Muthukumaravelu Velayoudame, Mandeep Singh, Michael Mar
  • Publication number: 20030148518
    Abstract: The present invention describes an improved method of Podophyllum hexandrum Royle through embryo culture technique by using B5 medium supplemented with 3% sucrose and 0.8% agar under initial dark conditions for embryo germination and initial embling growth followed by light/dark photoperiod regime for further embling development.
    Type: Application
    Filed: March 22, 2001
    Publication date: August 7, 2003
    Inventors: Amit Chandra Kharkwal, Om Prakash, Amita Bhattacharya, Paramvir Singh Ahuja
  • Patent number: 6449899
    Abstract: The present invention describes a method for inducing improved seed germination in a high altitude medicinal plant, Podophyllum hexandrum Royle through hot water treatment at 40° C.-100° C. for 30-120 seconds.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: September 17, 2002
    Assignee: Council of Scientific and Industrial Research
    Inventors: Amit Chandra Kharkwal, Om Prakash, Amita Bhattacharya, Pramod Kumar Nagar, Paramvir Singh Ahuja
  • Publication number: 20020124465
    Abstract: The present invention describes a method for inducing improved seed germination in a high altitude medicinal plant, Podophyllum hexandrum Royle through hot water treatment at 40° C.-100° C. for 30-120 seconds.
    Type: Application
    Filed: March 8, 2001
    Publication date: September 12, 2002
    Inventors: Amit Chandra Kharkwal, Om Prakash, Amita Bhattacharya, Pramod Kumar Nagar, Paramvir Singh Ahuja