Abstract: A microelectronic assembly may include a first microelectronic device, a second microelectronic device, a first signal link, a second signal link, and a first power connection. The first microelectronic device may include a first interface powered at a first voltage. The second microelectronic device may include a second interface powered at a second voltage. The first signal link may supply a first signal at the first voltage from the first interface to the second interface. The second signal link may supply a second signal at the second voltage from the second interface to the first interface. The first power connection may supply a first reference signal at the first voltage from the first interface to the second interface.

Abstract: A Universal Serial Bus 2.0 (USB2 or eUSB2) device includes an integrated circuit (IC) having a physical layer to send and receive data on a pair of signal lines, a repeater communicatively coupled to the physical layer via the pair of signal lines, and having a port to send and receive data on a second pair of signal lines and a power management unit to provide power to the physical layer and the repeater during an active state and to gate power to the physical layer and the repeater during a low power state.

Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.

Abstract: In one embodiment, a host controller includes a read controller to adjust internal clock timing based on a timer value associated with a first device and communicate information on an interconnect with the first device according to the adjusted clock timing. Other embodiments are described and claimed.

Abstract: A method and system implements a repeater in a link of a communication medium. The method and system enables a counter to count alternations of a clock signal received from a host or device over the link, compares a value of the counter to a reference count, adjusts a frequency selection based on the comparison of the value of the counter to the reference count, and locks the frequency selection in response to the counter matching the reference count.

Abstract: An apparatus is provided which comprises: a data circuitry to send and receive data to and from one or more devices coupled to the data circuitry via a first transmission line; and a first adjustable clock buffer coupled to the data circuitry, wherein the first adjustable clock buffer is to adjust a delay to an edge of a read clock according to a response time of the one or more devices.

Abstract: Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

Abstract: Techniques for mitigating voltage offsets are described herein. A method for mitigating voltage offset includes receiving, via a sensor, charging current information. The method also includes adjusting, via a common mode adjustment circuitry, a common mode voltage based on charging current information and a physical layer circuit mode.

Abstract: In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.

Abstract: Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

Abstract: Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.

Abstract: Methods and apparatuses relating to circuitry for multilane serial bus communications are described. In an embodiment, an apparatus includes a serial bus controller, upstream serial bus lanes, a single downstream serial bus lane, and a host/device lane controller. The serial bus controller is to send and receive data transmissions to and from serial bus devices. The upstream serial bus lanes correspond to the serial bus devices and are associated with serial port addresses. The host/device lane controller is to receive data transmissions through the upstream serial bus lanes and includes a port address assignment circuit and a multiplexer. The port address assignment circuit is to assign serial port addresses to data transmissions, to be included in data transmissions to identify the upstream serial bus lanes through which the data transmission was received. The multiplexer is to forward data transmissions from upstream serial bus lanes to the downstream serial bus lane.

Abstract: Embodiments of the present disclosure may relate to an I3C bus master that is to identify that an I3C bus with which the I3C bus master is coupled is to enter a serial peripheral interface (SPI) high data rate (HDR) mode. The I3C bus master may be further to communicate, in accordance with the SPI HDR mode, with an SPI slave device via an I3C serial data (SDA) line, an I3C serial clock (SCL) line, and a selection line. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatuses relating to circuitry to couple an embedded Universal Serial Bus (eUSB) circuit to a Universal Serial Bus (USB) transceiver interface circuit are described. In one embodiment, an apparatus includes an analog front end circuit to couple to a device; a transceiver interface circuit to couple to a serial bus controller; and an adapter circuit coupled between the analog front end circuit and the transceiver interface circuit to convert between a first protocol of the analog front end circuit and a second, different protocol of the transceiver interface circuit.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.

Abstract: Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design are disclosed herein. In embodiments, an apparatus may include common mode extraction circuitry to extract a common mode voltage from a USB input signal for a USB device, compare the common mode voltage with a reference voltage range and determine, based on the comparison, that the common mode voltage is outside of the reference voltage range. In the embodiments, the apparatus may further include processing circuitry to adjust the common mode voltage to within the reference voltage range. Other embodiments may be described and/or claimed.