Abstract: A universal interconnection scheme enables system architecture modularization with a hot-pluggable external computing module, such as a PC-on-a-card device using USB type-C technology. With the flexibility to interchange the system computing module with an external module, system performance can be augmented to fulfill the essential needs of the user, whether the system is a portable low-power tablet device, a smartphone, a wearable device such as an Internet of Things device, or a high-performance PC.

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

Abstract: In one example a electronic device comprises a body, a receptacle in the body comprising an opening to receive a memory card, wherein the receptacle comprises a first set of connectors configured to connect with pins on a memory card configured in accordance with a first standard and a second set of connectors configured to connect with pins on a memory card configured in accordance with a second standard. Other examples may be described.

Abstract: A system is disclosed for rendering a split multimedia content stream associated with a single program among networked playback devices in sync with each other. Splitting multimedia content allows, for example, two viewers of the same movie to hear the audio track in different languages, or presentation of related program information on a second screen. A presentation method disclosed ensures that the same program can be played in full or in part on multiple devices while maintaining audio and video synchronization among the devices. In one embodiment, synchronization is achieved by monitoring network latency and client system latency, and then incorporating latency information into a program clock reference (PCR) signal for transmission to a secondary playback device.

Abstract: Techniques for mitigating voltage offsets are described herein. A method for mitigating voltage offset includes receiving, via a sensor, charging current information. The method also includes adjusting, via a common mode adjustment circuitry, a common mode voltage based on charging current information and a physical layer circuit mode.

Abstract: A method for operating an augmented reality system includes acquiring video data from a camera sensor or video file, and identifying at least one region of interest within the video data. Augmented reality data is generated for the region of interest without receiving user input, with the augmented reality data being contextually related to the region of interest. The video data may be displayed with the augmented reality data superimposed thereupon in real time as the video data is acquired from the camera sensor or video file. The video data and the augmented reality data are stored in a non-conflated fashion. The video data may be displayed with updated AR content acquired for stored AR metadata during later playback. The method therefore allows the storage of AR ROI's and data from any suitable sensor as metadata, so that later retrieval is possible in the absence of additional processing.

Abstract: Techniques for port selection are described herein. The techniques may include an apparatus a transceiver including a plurality of ports. The apparatus includes a selector to select a port from among the plurality of ports. The port is selected to receive a repair operation to repair a basic input output system.

Abstract: A port of a first integrated circuit is coupled to a first communication path. Configuration information is communicated between a connector coupled to a second device and a second integrated circuit through the port and the first communication path. The port is decoupled from the first communication path. The port is coupled to a second communication path. Data is communicated between the connector and the second integrated circuit through the port and the second communication path.

Abstract: A system, method and apparatus for enabling a closed chassis debug control interface are disclosed. In one embodiment, the system comprises a debug mode control (DCI) unit; a Type-C connector; a Universal Serial Bus (USB) physical (phy) interface coupled to the connector; and interface logic coupled to the DCI unit and the USB phy interface to exchange debug control interface (DCI) signaling between the connector and the DCI unit.

Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.

Abstract: Described is an apparatus which comprises: a sensor to detect entrance of single-ended-zero (SE0) state on first and second data lines, and to detect exit of the SE0 state; and a clamp unit to clamp an overshoot or undershoot condition on the first or second data lines during the detected entrance and exit of the SE0 state.

Abstract: The present techniques include detecting a charger and remote host for a Type-C connector. An apparatus, system, and method are described herein. The apparatus comprises a USB Type-C port and a USB receiver detector. A charger and a remote host are differentiated based on the USB receiver detector.

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

Abstract: Described is an apparatus which comprises: a pre-driver coupled to a transmitter, the transmitter having a differential output; and a tuning circuit operable to couple to the differential output to tune the pre-driver of the transmitter according to a common mode noise signature of a common mode signal derived from the differential output.

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.