Patents by Inventor Amit KUNDU

Amit KUNDU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250148184
    Abstract: A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Shun Chen, Tzu-Ching Lin, Shu-Chin Tai, Amit Kundu, Yung-Chow Peng, Hung-Hsiang Lin, Yi-Peng Weng, Chung-Ting Lu
  • Patent number: 12292483
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.
    Type: Grant
    Filed: November 23, 2023
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng, Yi-Hsiang Wang
  • Patent number: 12244312
    Abstract: A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain/source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain/source paths connected in series to each other and to the first drain/source paths and having second gates connected to each other and to the first gates.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Shun Chen, Amit Kundu, Yung-Chow Peng
  • Patent number: 12228958
    Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Publication number: 20240394462
    Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Hsien Yu TSENG, Amit KUNDU, Chun-Wei CHANG, Szu-Lin LIU, Sheng-Feng LIU
  • Patent number: 12099792
    Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien Yu Tseng, Amit Kundu, Chun-Wei Chang, Szu-Lin Liu, Sheng-Feng Liu
  • Publication number: 20240186989
    Abstract: A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain/source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain/source paths connected in series to each other and to the first drain/source paths and having second gates connected to each other and to the first gates.
    Type: Application
    Filed: April 6, 2023
    Publication date: June 6, 2024
    Inventors: Yung-Shun Chen, Amit KUNDU, Yung-Chow Peng
  • Patent number: 11993867
    Abstract: Spun ABPBI fibers and a process for the preparing spun ABPBI fibers using a high molecular weight ABPBI dope solution suitable for spinning are provided. A process for preparing the high molecular weight ABPBI dope solution suitable for spinning is also provided. The spun ABPBI fibers can be used in the preparation of high temperature thermally resistant articles.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 28, 2024
    Assignee: GHARDA CHEMICALS LIMITED
    Inventors: Prakash D. Trivedi, Mathew Abraham, Amit Kundu
  • Publication number: 20240085491
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: AMIT KUNDU, JAW-JUINN HORNG, YI-HSIANG WANG
  • Publication number: 20240014136
    Abstract: A semiconductor device includes: first and second active regions (ARs) included correspondingly in abutting first and second analog cell regions, a region where the first and second analog cell regions abut (analog-cell-boundary (ACB) region) extending from about a top boundary of the first AR to about a bottom boundary of the second AR; via-to-PGBM_1st-segment contact structures (VBs) correspondingly being under the first or second ARs, a long axis of each VB and a short axis of each of the first and second ARs having about a same length; and a PG segment in a first buried metallization layer (PGBM_1st segment) under the VBs, the PGBM_1st segment underlapping a majority of each of the VBs, and a Y-midline of the PGBM_1st segment being at or proximal to where the first and second analog cell regions abut and thus being at or proximal to a middle of the ACB region.
    Type: Application
    Filed: January 23, 2023
    Publication date: January 11, 2024
    Inventors: Ming-Cheng SYU, Yu-Tao YANG, Chung-Ting LU, Po-Zeng KANG, Amit KUNDU, Wen-Shen CHOU, Yung-Chow PENG
  • Patent number: 11860238
    Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng, Yi-Hsiang Wang
  • Publication number: 20230367352
    Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Publication number: 20230334220
    Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Hsien Yu TSENG, Amit KUNDU, Chun-Wei CHANG, Szu-Lin LIU, Sheng-Feng LIU
  • Publication number: 20230317806
    Abstract: A method of making a semiconductor device includes forming an active device region in a substrate. The method further includes forming a first transistor in the active device region, the first transistor including a first channel region a first source region and a first drain region. The method further includes forming a guard ring region outside the active device region. The method further includes forming a second transistor in the guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.
    Type: Application
    Filed: May 24, 2023
    Publication date: October 5, 2023
    Inventors: Amit KUNDU, Jaw-Juinn HORNG
  • Patent number: 11755051
    Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 11687698
    Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien Yu Tseng, Amit Kundu, Chun-Wei Chang, Szu-Lin Liu, Sheng-Feng Liu
  • Patent number: 11677007
    Abstract: A layout of a semiconductor device stored on a non-transitory computer-readable medium includes a first transistor in an active device region, the first transistor comprising a first channel region a first source region and a first drain region. The layout further includes a second transistor in a guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Publication number: 20220357759
    Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 11474552
    Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Publication number: 20220283601
    Abstract: Systems and methods are provided for generating a temperature compensated reference voltage. A temperature compensation circuit may include a proportional-to-absolute temperature (PTAT) circuit, and a complementary-to-absolute temperature (CTAT) circuit, with the PTAT circuit and the CTAT circuit including at least one common metal-oxide-semiconductor field-effect transistor (MOSFET) and being configured to collectively generate a reference voltage in response to a regulated current input. The PTAT circuit may be configured to produce an increase in magnitude of the reference voltage with an increase of temperature, and the CTAT circuit may be configured to generated a decrease in magnitude of the reference voltage with the increase of temperature, wherein the increase in magnitude of the reference voltage produced by the PTAT circuit is at least partially offset by the decrease in magnitude of the reference voltage produced by the CTAT circuit.
    Type: Application
    Filed: June 30, 2021
    Publication date: September 8, 2022
    Inventors: Amit Kundu, Jaw-Juinn Horng