Patents by Inventor Amit KUNDU
Amit KUNDU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923572Abstract: A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region, a first gate structure across the first channel region, and a first source region and a first drain region on opposite sides of the first channel region. The second transistor includes a second channel region, a second gate structure across the second channel region, a second source region and a second drain region on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.Type: GrantFiled: May 29, 2019Date of Patent: February 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Amit Kundu, Jaw-Juinn Horng
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Patent number: 10867109Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.Type: GrantFiled: May 29, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsien Yu Tseng, Chun-Wei Chang, Szu-Lin Liu, Amit Kundu, Sheng-Feng Liu
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Publication number: 20200105887Abstract: A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region, a first gate structure across the first channel region, and a first source region and a first drain region on opposite sides of the first channel region. The second transistor includes a second channel region, a second gate structure across the second channel region, a second source region and a second drain region on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.Type: ApplicationFiled: May 29, 2019Publication date: April 2, 2020Inventors: Amit KUNDU, Jaw-Juinn HORNG
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Publication number: 20200065451Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.Type: ApplicationFiled: May 29, 2019Publication date: February 27, 2020Inventors: Hsien YU TSENG, Chun-Wei CHANG, Szu-Lin LIU, Amit KUNDU, Sheng-Feng LIU
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Publication number: 20190131299Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.Type: ApplicationFiled: December 20, 2018Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Amit Kundu, Chia-Hsin Hu, Jaw-Juinn Horng
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Patent number: 10268228Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.Type: GrantFiled: March 10, 2017Date of Patent: April 23, 2019Inventors: Amit Kundu, Jaw-Juinn Horng
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Patent number: 10163899Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.Type: GrantFiled: November 30, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Amit Kundu, Chia-Hsin Hu, Jaw-Juinn Horng
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Patent number: 10090221Abstract: A method of forming a semiconductor device includes implanting dopants in a first region of the semiconductor device to form a source region. The method further includes forming a guard ring in a second region of the semiconductor device, the guard ring being separated from the source region by a first spacing. The method further includes depositing a first heat conductive layer over the source region, wherein the first heat conductive layer is directly coupled to the source region and directly coupled to the guard ring. The first heat conductive layer is configured to dissipate heat generated by the semiconductor device from the source region to the guard ring.Type: GrantFiled: December 6, 2016Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Amit Kundu, Jaw-Juinn Horng, Chung-Hui Chen
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Publication number: 20180151562Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.Type: ApplicationFiled: November 30, 2016Publication date: May 31, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Amit KUNDU, Chia-Hsin Hu, Jaw-Juinn Horng
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Patent number: 9864393Abstract: In some embodiments, a circuit includes a first transistor, a second transistor, a resistive device and an amplifier. The first transistor includes a first drain and a first gate. The second transistor includes a second drain and a second gate. The resistive device is coupled between the first gate and the second gate. The amplifier includes a first input coupled to the first drain and a second input coupled to the second drain. The amplifier is configured to keep a voltage level at the first drain and that at the second drain equal to each other.Type: GrantFiled: February 2, 2016Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDInventors: Jaw-Juinn Horng, Amit Kundu
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Patent number: 9791879Abstract: A voltage reference circuit is provided that includes a first circuit, a second circuit and a third circuit. The first circuit has a first MOS transistor pair and the second circuit has a second MOS transistor pair. The first circuit is configured to provide a first voltage component that changes at a first rate having a first slope as a temperature to which the voltage reference circuit is subjected changes. The second circuit is configured to provide a second voltage component that changes at a second rate having a second slope as the temperature changes. The third circuit is configured to use the first voltage component and the second voltage component to generate the reference voltage component that changes at a fifth rate having a fifth slope as the temperature changes. The fifth slope is substantially equal to zero to promote insensitivity of the reference voltage component to temperature changes.Type: GrantFiled: October 25, 2013Date of Patent: October 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jaw-Juinn Horng, Amit Kundu, Chung-Hui Chen, Yung-Chow Peng
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Publication number: 20170185097Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.Type: ApplicationFiled: March 10, 2017Publication date: June 29, 2017Inventors: Amit Kundu, Jaw-Juinn Horng
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Publication number: 20170084512Abstract: A method of forming a semiconductor device includes implanting dopants in a first region of the semiconductor device to form a source region. The method further includes forming a guard ring in a second region of the semiconductor device, the guard ring being separated from the source region by a first spacing. The method further includes depositing a first heat conductive layer over the source region, wherein the first heat conductive layer is directly coupled to the source region and directly coupled to the guard ring. The first heat conductive layer is configured to dissipate heat generated by the semiconductor device from the source region to the guard ring.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Amit KUNDU, Jaw-Juinn HORNG, Chung-Hui CHEN
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Patent number: 9594390Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.Type: GrantFiled: November 26, 2014Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Amit Kundu, Jaw-Juinn Horng
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Patent number: 9536790Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.Type: GrantFiled: January 14, 2014Date of Patent: January 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Amit Kundu, Jaw-Juinn Horng, Chung-Hui Chen
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Patent number: 9536876Abstract: A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.Type: GrantFiled: August 1, 2013Date of Patent: January 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Chow Peng, Amit Kundu, Szu-Lin Liu, Jaw-Juinn Horng
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Publication number: 20160357212Abstract: In some embodiments, a circuit includes a first transistor, a second transistor, a resistive device and an amplifier. The first transistor includes a first drain and a first gate. The second transistor includes a second drain and a second gate. The resistive device is coupled between the first gate and the second gate. The amplifier includes a first input coupled to the first drain and a second input coupled to the second drain. The amplifier is configured to keep a voltage level at the first drain and that at the second drain equal to each other.Type: ApplicationFiled: February 2, 2016Publication date: December 8, 2016Inventors: JAW-JUINN HORNG, AMIT KUNDU
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Patent number: 9378314Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.Type: GrantFiled: August 25, 2014Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Amit Kundu, Jaw-Juinn Horng, Yung-Chow Peng, Shih-Cheng Yang, Chung-Kai Lin
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Publication number: 20160147245Abstract: A voltage reference circuit is provided. In some embodiments, the voltage reference circuit includes a MOS stack that includes two or more MOS transistors having a substantially same voltage threshold. The voltage reference circuit is configured to generate, via the MOS stack, a first voltage waveform having a first temperature co-efficient and a second voltage waveform having a second temperature co-efficient. In some embodiments, the first temperature co-efficient has a polarity that is opposite a polarity of the second temperature co-efficient. In some embodiments, the first voltage waveform and the second voltage waveform are used to generate a reference voltage waveform, where the reference voltage waveform is substantially temperature independent due to the opposite polarities of the first temperature co-efficient and the second temperature co-efficient.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: Amit Kundu, Jaw-Juinn Horng
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Publication number: 20150200249Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Amit KUNDU, Jaw-Juinn HORNG, Chung-Hui CHEN