Patents by Inventor Amit Merchant
Amit Merchant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11307902Abstract: A method for orchestrating a provisioning of a computer workload includes determining characteristics of a computing pattern, determining health data of a computing environment based on the characteristics of the computing pattern, determining a confidence score based on the health data, and determining whether to proceed with provisioning the computer workload based on the confidence score.Type: GrantFiled: September 30, 2020Date of Patent: April 19, 2022Assignee: KYNDRYL, INC.Inventors: Hariharan N. Venkitachalam, Harish Bhatt, Amit Merchant, Prashant Pareek
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Publication number: 20220100564Abstract: A method for orchestrating a provisioning of a computer workload includes determining characteristics of a computing pattern, determining health data of a computing environment based on the characteristics of the computing pattern, determining a confidence score based on the health data, and determining whether to proceed with provisioning the computer workload based on the confidence score.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Hariharan N. Venkitachalam, Harish Bhatt, Amit Merchant, Prashant Pareek
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Patent number: 9178939Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.Type: GrantFiled: June 20, 2014Date of Patent: November 3, 2015Assignee: International Business Machines CorporationInventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
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Patent number: 9178770Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.Type: GrantFiled: December 23, 2013Date of Patent: November 3, 2015Assignee: International Business Machines CorporationInventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
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Publication number: 20150178520Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.Type: ApplicationFiled: June 20, 2014Publication date: June 25, 2015Inventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
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Publication number: 20150180720Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Applicant: International Business Machines CorporationInventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
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Patent number: 8898435Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.Type: GrantFiled: November 29, 2013Date of Patent: November 25, 2014Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
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Patent number: 8898434Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.Type: GrantFiled: November 11, 2011Date of Patent: November 25, 2014Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
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Publication number: 20140089637Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.Type: ApplicationFiled: November 29, 2013Publication date: March 27, 2014Applicant: International Business Machines CorporationInventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
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Publication number: 20130124826Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
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Patent number: 7366879Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.Type: GrantFiled: September 27, 2004Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
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Patent number: 7353370Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.Type: GrantFiled: January 20, 2005Date of Patent: April 1, 2008Assignee: Intel CorporationInventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
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Patent number: 7219349Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.Type: GrantFiled: March 2, 2004Date of Patent: May 15, 2007Assignee: Intel CorporationInventors: Amit A. Merchant, Darrell D. Boggs, David J. Sager
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Patent number: 7200737Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.Type: GrantFiled: December 29, 1999Date of Patent: April 3, 2007Assignee: Intel CorporationInventors: Amit A. Merchant, Darrell D. Boggs, David J. Sager
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Patent number: 7089409Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.Type: GrantFiled: October 23, 2003Date of Patent: August 8, 2006Assignee: Intel CorporationInventors: Amit A. Merchant, Darrell D. Boggs, David J. Sager
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Patent number: 7039794Abstract: A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the second thread. Responsive to the detection of the event handling point for the second thread, at least a first event handler is invoked to handle at least the first pending event.Type: GrantFiled: September 18, 2002Date of Patent: May 2, 2006Assignee: Intel CorporationInventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
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Publication number: 20050132376Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.Type: ApplicationFiled: January 20, 2005Publication date: June 16, 2005Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
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Patent number: 6889319Abstract: A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.Type: GrantFiled: December 9, 1999Date of Patent: May 3, 2005Assignee: Intel CorporationInventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
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Publication number: 20050038980Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.Type: ApplicationFiled: September 27, 2004Publication date: February 17, 2005Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
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Patent number: 6792446Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.Type: GrantFiled: February 1, 2002Date of Patent: September 14, 2004Assignee: Intel CorporationInventors: Amit A. Merchant, Darrell D. Buggs, David J. Sager