Patents by Inventor Amit Merchant

Amit Merchant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9178939
    Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
  • Patent number: 9178770
    Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
  • Publication number: 20150178520
    Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.
    Type: Application
    Filed: June 20, 2014
    Publication date: June 25, 2015
    Inventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
  • Publication number: 20150180720
    Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: International Business Machines Corporation
    Inventors: Amit Merchant, Venkatesh Patil, Praveen Vyas
  • Patent number: 8898434
    Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: November 25, 2014
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
  • Patent number: 8898435
    Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: November 25, 2014
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
  • Publication number: 20140089637
    Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.
    Type: Application
    Filed: November 29, 2013
    Publication date: March 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
  • Publication number: 20130124826
    Abstract: A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Amit Merchant, Dipankar Sarma, Vaidyanathan Srinivasan
  • Patent number: 7366879
    Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
  • Patent number: 7353370
    Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
  • Patent number: 7219349
    Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Amit A. Merchant, Darrell D. Boggs, David J. Sager
  • Patent number: 7200737
    Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventors: Amit A. Merchant, Darrell D. Boggs, David J. Sager
  • Patent number: 7089409
    Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Amit A. Merchant, Darrell D. Boggs, David J. Sager
  • Patent number: 7039794
    Abstract: A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the second thread. Responsive to the detection of the event handling point for the second thread, at least a first event handler is invoked to handle at least the first pending event.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
  • Publication number: 20050132376
    Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.
    Type: Application
    Filed: January 20, 2005
    Publication date: June 16, 2005
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
  • Patent number: 6889319
    Abstract: A method includes maintaining a state machine to provide a multi-bit output, each bit of the multi-bit output indicating a respective status for an associated thread of multiple threads being executed within a multithreaded processor. Status for a first thread is detected, responsive to which a functional unit within the multithreaded processor is configured in accordance with the multi-bit output of the state machine.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: May 3, 2005
    Assignee: Intel Corporation
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
  • Publication number: 20050038980
    Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.
    Type: Application
    Filed: September 27, 2004
    Publication date: February 17, 2005
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
  • Patent number: 6792446
    Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: Amit A. Merchant, Darrell D. Buggs, David J. Sager
  • Publication number: 20040172523
    Abstract: A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
    Type: Application
    Filed: March 2, 2004
    Publication date: September 2, 2004
    Inventors: Amit A. Merchant, Darrell D. Buggs, David J. Sager
  • Patent number: 6785803
    Abstract: A technique is provided for breaking a stalled condition or livelock in a processor having a replay queue. A livelock or stalled condition is detected. One or more instructions are temporarily stored in a replay queue. A release or break in the livelock or stalled condition is detected, and the instructions are then unloaded from the replay queue for replay or re-execution. For a multi-threaded processor, a stall is detected in one of the threads. Instructions of the stalled thread are temporarily stored in a replay queue, except the oldest instruction of the stalled thread which is allowed to replay or re-execute. This allows other threads to have access to execution and replay resources. Eventually, the oldest instruction will execute and retire, which breaks or releases the stalled thread. The instructions stored in the replay queue are then unloaded from the replay queue.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Amit A. Merchant, David J. Sager, James D. Allen