Abstract: An efficient method for handling multiple conflicting snoop requests with minimal stalling on the external bus by using blocking conditions to maintain and update a snoop queue for maintaining cache coherence in a computer system with caching units. An entry in a snoop queue is allocated to a snoopable request which has an associated snoop address. The snoop address is compared with addresses corresponding to previously allocated entries stored in the snoop queue. A block condition is set if there is a match between the snoop address and one or more of the addresses stored in the snoop queue. One or more history bits are set in the snoop queue indicating a chronological ordering of the entry in the snoop queue. A snoop operation corresponding to the snoop request is blocked until the block condition is cleared.

Abstract: A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.

Abstract: A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a bus clock signal having a plurality of cycles. To indicate snoop stretching, during a first cycle a first snooping agent asserts both a HIT# bus signal and a HITM# bus signal together to indicate that the first snooping agent must delay assertion of valid snoop results for a predetermined snoop period. During a later cycle, to indicate the end of the snoop stretch, the first snooping agent deasserts the assertion of both the HIT# and HITM# signals together and asserts its valid snoop results. The HIT# and HITM# signals alone each represent valid snoop results.

Abstract: Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent.

Abstract: A method of preconditioning a nonvolatile memory array including a first memory cell and a second memory cell. Preconditioning begins by applying an initial precondition pulse to all memory cells in the nonvolatile memory array without pausing to perform precondition verification. After this first step, precondition verification begins. The voltage level of the first memory cell is sensed and compared to a selected voltage level. If the threshold voltage of the first memory cell is below the selected voltage, the first memory cell did not precondition verify. In that case, another precondition pulse is then applied to the first memory cell. Application of precondition pulses and precondition verification continues until the first memory cell verifies as preconditioned. Attention turns to the second memory cell after the first memory cell precondition verifies. If the second memory cell does not precondition verify another precondition pulse is applied to the second memory cell.

Abstract: Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high enough to prevent bitline leakage. The circuitry includes a sense amplifier for comparing the threshold voltage of a memory cell within the memory array to a selected reference threshold voltage level. The sense amplifier indicates whether the array memory cells exceeds the selected reference threshold voltage level. Selection circuitry couples two different reference cells to the sense amplifier, each having a different threshold voltage level. One of the reference cells has a normal threshold voltage level; i.e., a threshold voltage level to which good cells should be preconditioned.

Abstract: A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.

Abstract: Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure.

Abstract: A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is overerased. A programming pulse is applied to the second cell if it is overerased. Afterward, if either of the cells was overerased then the repair pulse voltage level is incremented. These steps are repeated until none of the cells on the column is identified as overerased.