Patents by Inventor Amitay Levi

Amitay Levi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10679685
    Abstract: A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed by biasing a selected word line, a selected bit line, and a selected source line coupled to corresponding column of memory cells coupled to the selected bit line, and by counter biasing one or more selected source lines coupled to one or more other columns of memory cells coupled to the selected bit line.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 9, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Loc Hoang, Amitay Levi
  • Patent number: 10658425
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 19, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Publication number: 20200127052
    Abstract: A memory array for data recording that includes a selector transistor electrically connected with a two terminal resistive memory element such as a magnetic tunnel junction (MTJ) element. The selector transistor comprises a semiconductor column formed by selective epitaxial growth on a semiconductor surface. The semiconductor column is at least partially surrounded by a gate dielectric layer and an electrically conductive gate structure arranged such that the gate dielectric is between the electrically conducive gate structure and the semiconductor column. The selective epitaxial growth of the semiconductor column allows the semiconductor column to have a very low electrical resistance in an “on” state which allows the selector transistor to provide a high electrical current to the two terminal resistive memory element for reliable switching during data writing.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Andrew J. Walker, Dafna Beery, Peter Cuevas, Amitay Levi
  • Patent number: 10629649
    Abstract: According to one embodiment, a method of forming a magnetic memory device includes forming a source region including a first semiconductor material having a first conductivity above a substrate, forming an array of three-dimensional (3D) structures above the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material on the channel material on the surface of at least one sidewall of each 3D structure, forming a first isolation region in the cavity region above the substrate, forming a first gate region above the first isolation region in the cavity region, and forming a second isolation region above the first gate region, wherein a nth gate region is formed above a (n+1) isolation region thereafter until a top of the array of 3D structures, wherein each nth gate region is coupled to each nth perpendicular magnetic tunnel junction sensor of each 3D structure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 21, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10614867
    Abstract: A method for forming an array of very small pillar structures having a very small feature size that is smaller than the resolution limit of photolithographic process available for patterning such structures. The method involves forming an array of silicon pillar structures over a layer of material that will ultimately form the pillar structures. The array of silicon pillar structures is repeatedly oxidized to form a layer of silicon oxide at an outer surface of the silicon pillar structures and then etched to remove the outer layer of oxide, thereby reducing the features size (i.e. diameter) of the silicon pillar structure. A final oxidation process entirely oxidizes the remaining silicon pillar structures, leaving an array of small silicon oxide pillar structures that can be used as a mask for patterning underlying layers, including the underlying pillar material. The process is especially useful for forming an array of magnetic memory pillars.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 7, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi
  • Publication number: 20200043537
    Abstract: A method for forming an array of very small pillar structures having a very small feature size that is smaller than the resolution limit of photolithographic process available for patterning such structures. The method involves forming an array of silicon pillar structures over a layer of material that will ultimately form the pillar structures. The array of silicon pillar structures is repeatedly oxidized to form a layer of silicon oxide at an outer surface of the silicon pillar structures and then etched to remove the outer layer of oxide, thereby reducing the features size (i.e. diameter) of the silicon pillar structure. A final oxidation process entirely oxidizes the remaining silicon pillar structures, leaving an array of small silicon oxide pillar structures that can be used as a mask for patterning underlying layers, including the underlying pillar material. The process is especially useful for forming an array of magnetic memory pillars.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Gian Sharma, Amitay Levi
  • Patent number: 10497415
    Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 3, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Gian Sharma, Amitay Levi
  • Publication number: 20190355896
    Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10468293
    Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 5, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10460778
    Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 29, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Gian Sharma, Marcin Gajek, Kadriye Deniz Bozdag, Girish Jagtiani, Eric Michael Ryan, Michail Tzoufras, Amitay Levi, Andrew J. Walker
  • Publication number: 20190311956
    Abstract: An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.
    Type: Application
    Filed: January 29, 2019
    Publication date: October 10, 2019
    Inventors: Gian Sharma, Amitay Levi, Kuk-Hwan Kim
  • Patent number: 10438996
    Abstract: Methods of fabricating devices including arrays of integrated Magnetic Tunnel Junctions (MTJs) and corresponding selectors in an array of cells. The array of cells can include a plurality of source lines disposed in columns, set of selectors coupled to respective source lines, MJT structures coupled to respective selectors and a plurality of bit lines disposed in rows and coupled to respective sets of MTJ structures. The array of cells can also include buffers coupled between respective selectors and respective MTJ structures. In addition, multiple arrays can be fabricated on top of each other to implement vertical three-dimensional (3D) MTJ devices.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 8, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Andy Walker, Amitay Levi
  • Patent number: 10438999
    Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 8, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Patent number: 10431628
    Abstract: According to one embodiment, a method includes forming a drain contact above a channel, each having a hollow circular cross-section thereof along a plane perpendicular to a film thickness direction, forming gate dielectric layers on sides of the drain contact and the channel, forming a source line positioned below the channel that is electrically coupled to a plurality of channels in a direction along the plane, forming gate layers on sides of the gate dielectric layers, where an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane, and where an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane, forming an electrode above the upper surface of the drain contact, and forming a fourth insulative layer on sides of the electrode along the plane.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 1, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Marcin Gajek, Dafna Beery, Amitay Levi
  • Publication number: 20190287596
    Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device a magnetic memory component and a current selector component coupled to the magnetic memory component. The current selector component includes a first transistor having a first gate with a corresponding first threshold voltage. The first transistor comprises a charge storage layer configured to selectively store charge so as to adjust a current through the first transistor. The memory device further includes control circuitry configured to determine a bit error rate of the magnetic memory component and adjust a charge stored in the charge storage layer based on the determined bit error rate.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Inventors: Kuk-Hwan Kim, Gian Sharma, Amitay Levi
  • Patent number: 10355046
    Abstract: According to one embodiment, an apparatus includes a bottom electrode layer positioned above a substrate in a film thickness direction, a source layer positioned above the bottom electrode layer in the film thickness direction, an impact ionization channel (i-channel) layer positioned above the source layer in the film thickness direction, a drain layer positioned above the i-channel layer in the film thickness direction, an upper electrode layer positioned above the drain layer in the film thickness direction that forms a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is positioned closer to the drain layer than the source layer. Other apparatuses are described in accordance with more embodiments.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10355045
    Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 10355047
    Abstract: A method, according to one embodiment, includes: forming an annular cylindrical channel from a single block of electrically conductive material; forming an oxide layer over exposed surfaces of the annular cylindrical channel and exposed surfaces of the block of electrically conductive material; removing a portion of the oxide layer from an exterior base of the annular cylindrical channel, thereby forming a source contact recess which surrounds the base of the annular cylindrical channel; ion-implanting the exposed electrically conductive material substrate at a base of the source contact recess; and depositing a silicide material in the source contact recess, thereby forming a source contact tab.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 16, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Publication number: 20190214430
    Abstract: Methods of fabricating devices including arrays of integrated Magnetic Tunnel Junctions (MTJs) and corresponding selectors in an array of cells. The array of cells can include a plurality of source lines disposed in columns, set of selectors coupled to respective source lines, MJT structures coupled to respective selectors and a plurality of bit lines disposed in rows and coupled to respective sets of MTJ structures. The array of cells can also include buffers coupled between respective selectors and respective MTJ structures. In addition, multiple arrays can be fabricated on top of each other to implement vertical three-dimensional (3D) MTJ devices.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Kuk-Hwan KIM, Dafna BEERY, Andy WALKER, Amitay LEVI
  • Publication number: 20190214551
    Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker