Abstract: According to one embodiment, a method includes forming, at a low temperature, a thin film transistor structure above a flexible substrate in a film thickness direction. The low temperature is less than about 200° C., and the thin film transistor structure includes a contact pad on a lower or upper surface thereof. The method also includes forming, at a high temperature, a perpendicular magnetic tunnel junction (pMTJ) structure above a rigid substrate. The high temperature is greater than about 200° C. The method also includes removing the rigid substrate from below the pMTJ structure and bonding, at the low temperature, the pMTJ structure to the thin film transistor structure using an adhesion layer. Other methods of forming flexible substrates for mounting pMTJs and systems thereof are described in accordance with more embodiments.

Abstract: According to one embodiment, an apparatus includes: a substrate, an array of 3D structures, where each 3D structure includes a source region having a first conductivity, a series of layers positioned in a vertical direction, a channel material on a surface of at least one sidewall of each 3D structure, and a gate dielectric material on the channel material. The series of layers includes a dielectric layer positioned above the substrate, a plurality of a set of MTJ layers positioned above the dielectric layer, and a buffer layer positioned in between the dielectric layer and each set of MTJ layers thereof. The magnetic memory device further includes an isolation region positioned between the 3D structures and at least one gate region positioned above the isolation region, where each gate region is coupled to at least one sidewall of each 3D structure.

Abstract: A method of forming a cylindrical vertical transistor; the method, according to one embodiment, includes: forming a cylindrical pillar from a single block of silicon, forming an oxide layer over an exterior of the cylindrical pillar and exposed surfaces of the block of silicon, coating the oxide layer with a spin-on-glass (SOG), depositing a source mask over a majority of the SOG coating, and removing a portion of the SOG coating and underlying oxide layer, where the portion removed is defined by the source mask. Other systems and methods are also described in additional embodiments herein which provide various different improved processes of forming the cylindrical gate contacts, the source contacts, and/or the drain contacts for vertical transistor structures which also include the aforementioned cylindrical pillar channel structures and cylindrical gate in comparison to conventional surface transistor structures.

Abstract: According to one embodiment, a method includes forming a first insulative layer above a bottom surface of a groove and along inner sidewalls thereof, forming a source line layer within the groove of the substrate, forming a first dielectric layer on outer sides of a middle portion of the source line layer, forming a buffer layer on outer sides of the first dielectric layer, forming a gate terminal above the source line layer, forming a gate dielectric layer between the source line layer and the gate terminal and on outer sides of the lower portion of the gate terminal, forming a drain terminal including strained Si on outer sides of the first dielectric layer, and forming a relaxed buffer layer on outer sides of the upper portion of the source line layer and outer sides of the drain terminal, with the gate terminal extending beyond the relaxed buffer layer thickness.

Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.

Abstract: According to one embodiment, a method of forming a magnetic memory device includes forming a source region including a first semiconductor material having a first conductivity above a substrate, forming an array of three-dimensional (3D) structures above the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material on the channel material on the surface of at least one sidewall of each 3D structure, forming a first isolation region in the cavity region above the substrate, forming a first gate region above the first isolation region in the cavity region, and forming a second isolation region above the first gate region, wherein a nth gate region is formed above a (n+1) isolation region thereafter until a top of the array of 3D structures, wherein each nth gate region is coupled to each nth perpendicular magnetic tunnel junction sensor of each 3D structure.

Abstract: A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.

Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.

Abstract: A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed by biasing a selected word line, a selected bit line, and a selected source line coupled to corresponding column of memory cells coupled to the selected bit line, and by counter biasing one or more selected source lines coupled to one or more other columns of memory cells coupled to the selected bit line.

Abstract: According to one embodiment, a method includes forming an etch-stop layer above a substrate, forming a matrix layer above the etch-stop layer, forming a set of pillars above the matrix layer, the set of pillars having a predefined spacing therebetween along a plane in an element width direction and an element depth direction, the plane being normal to a film thickness direction, forming a functionalization layer above the pillars, along sides of the pillars, and above the matrix layer, forming first diblock copolymer layers above the functionalization layer, the first diblock copolymer layers self-segregating into a first polymer and a second polymer in a first pattern, removing the first polymer from the first diblock copolymer layers to create a first mask layer, and removing portions of the matrix layer to expose portions of the etch-stop layer positioned therebelow and create a second pattern in the matrix layer.

Abstract: The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a magnetic memory component; and (2) a current selector component coupled to the magnetic memory component, the current selector component including: (a) a first transistor having a first gate with a corresponding first threshold voltage; and (b) a second transistor having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage; where the second transistor is coupled in parallel with the first transistor.

Abstract: According to one embodiment, a method includes forming a bottom electrode layer above a substrate in a film thickness direction, forming a source layer above the bottom electrode layer in the film thickness direction, forming an impact ionization channel (i-channel) layer above the source layer in the film thickness direction, forming a drain layer above the i-channel layer in the film thickness direction, forming an upper electrode layer above the drain layer in the film thickness direction to form a stack that includes the bottom electrode layer, the source layer, the i-channel layer, the drain layer, and the upper electrode layer, and forming a gate layer positioned on sides of the i-channel layer along a plane perpendicular to the film thickness direction in an element width direction. The gate layer is formed in a position closer to the drain layer than the source layer.

Abstract: A processor-implemented method, according to one embodiment, includes: activating a subset of a plurality of p-MTJ cells oriented in one or more columns of a MRAM array. Activating the subset of p-MTJ cells includes: applying a first voltage to a gate terminal of the transistor in each of the p-MTJ cells in parallel, applying a second voltage to a first end of the MTJ sensor in each of the p-MTJ cells in parallel, and applying a third voltage to a drain terminal of the transistor in each of the p-MTJ cells in parallel. The processor-implemented method also includes: monitoring the activated subset of p-MTJ cells, determining whether any of the activated p-MTJ cells have failed, and in response to determining that an activated p-MTJ cell has failed, physically locating the failed p-MTJ cell. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.

Abstract: In one embodiment, an apparatus includes lower electrodes positioned below a surface of a substrate, the substrate including crystalline Si, a plurality of strap regions positioned above the lower electrodes and below sets of pillars of Si, the pillars rising above the substrate, the sets of pillars being aligned in a first direction along a plane perpendicular to a film thickness direction, and the strap regions extending above a surface of the substrate, silicide junctions positioned between each of the strap regions and a corresponding lower electrode positioned therebelow, upper electrodes positioned above each of the pillars, gate dielectric layers positioned on sides of the pillars to a height greater than a lower edge of the upper electrodes, and gate layers positioned on sides of the gate dielectric layers in a second direction along the plane and perpendicular to the first direction that transverse a plurality of sets of pillars.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.