Abstract: Methods, systems, and devices for techniques for improved data transfer are described. As part of a data transfer operation from a first set of memory cells of a memory device to a second set of memory cells of the memory device, a memory controller of may read a set of data units from the first set of memory cells. The memory device 240 may transmit the set of data units to the memory controller. The memory controller may decode the set of data units, and, in some cases, may generate one or more corrected data units. The memory controller may then generate parity information for the set of data units, and may encode and write the parity information, along with any corrected data units, to the second set of memory cells of the memory device without transferring the uncorrected data units.

Abstract: Methods, systems, and devices for synchronizing operations between decks of a memory system are described. In some examples, a memory system may determine a PEC difference between sister decks of physical blocks of the memory system. A memory system controller may associate the sister decks with respective virtual blocks. The controller may scan each virtual block of the memory system to determine which blocks are to be recycled, and may generate a list of virtual blocks having a VPC that satisfies a first threshold. In some cases, the controller may perform one or more threshold comparisons to determine whether to perform the maintenance operation on the first sister deck or both the first sister deck and the second sister deck.

Abstract: Methods, systems, and devices for corrective read techniques for memory systems are described. A memory system may determine respective ranges of stored charge for each first memory cell of a set of first memory cells associated with a first word line. The ranges of stored charge may correspond to respective written states of each first memory cell. The memory system may read a set of second memory cells associated with a second word line based on biasing each second memory cell of the plurality of second memory cells with a respective set of one or more read voltages. The one or more read voltages may be based on the respective ranges of stored charge of the first memory cells. The memory system may output data associated with the second word line based on the reading of the plurality of second memory cells.

Abstract: Methods, systems, and devices for transferring valid data using a system latch are described. The operations described herein may include sensing valid data across a first set of planes associated with a first set of memory blocks of a non-volatile memory system. In response to sensing the valid data, the valid data may be stored to a latch of the non-volatile memory system based on an order of sensing the valid data across the first set of planes. The valid data may be written across a second set of planes associated with a second set of memory blocks of the non-volatile memory system based on the order of sensing the valid data across the first set of planes. In some cases, writing the valid data from the latch may be based on determining that a threshold associated with a duration corresponding to sensing the valid data has been satisfied.

Abstract: Methods, systems, and devices for an erase operation for a memory system are described. The memory system may perform, on a block of memory cells, a first portion of an erase operation. After performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. In response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. In response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. As such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.

Abstract: Methods, systems, and devices for detection and retirement of defective blocks are described. Techniques described herein may enable a memory system to determine if a block of memory cells may be partially retired. For example, the memory system may determine if an error correction counter has satisfied a first threshold or if a bit error rate (BER) of the block of memory cells satisfies a second threshold. The memory system may determine if a BER of one or more word lines of a first deck of the block of memory cells and a BER of one or more word lines of neighboring decks of the block of memory cells satisfy respective thresholds. The memory system may accordingly determine whether to refrain from retiring the block of memory cells, to partially retire the block of memory cells, or to fully retire the block of memory cells.

Abstract: Methods, systems, and devices for reducing latency for data recovery procedures in memory systems are described. A memory system may initialize an error recovery procedure in response to a failure to correct data read the memory system during a first read operation, where the first read operation is performed using a first read voltage. In response to the initialization, the memory system may identify, as part of the error recovery procedure, a first read offset from multiple read offsets according to a first syndrome weight generated as part of an attempt to correct the data. Accordingly, the memory system may perform, as part of the error recovery procedure, a second read operation to obtain the data, where the second read operation may be performed using a second read voltage that is the first read voltage modified by the first read offset.

Abstract: The present disclosure configures a memory sub-system controller to perform reads in a memory sub-system using predictive read offsets. The controller receives a request to read a word line group (WLG) of a set of memory components. The controller stores a table that associates a first read level offset with a first region of the WLG and a second read level offset with a second region of the WLG. The controller reads a first set of data stored in the first region of the WLG using the first read level offset stored in the table and reads a second set of data stored in the second region of the WLG using the second read level offset stored in the table.

Abstract: Methods, systems, and devices for reducing charge migration in a memory system are described. The memory system may receive a command to program a first set of memory cells with first data. The memory system may generate a scrambling seed to scramble the first data. Before programming the scrambled data, the memory system may compare a first set of states in the scrambled data with a second set of states in second data to determine an aggregate difference between the sets of states. If the aggregate difference is less than a threshold, the memory system may program the first set of memory cells with the first data. If the aggregate difference is greater than a threshold, the memory system may generate a new scrambling seed to rescramble the first data and determine a new aggregate difference by comparing states of the rescrambled data to the states of the second data.

Abstract: Methods, systems, and devices for redundant array parity information storage are described. A memory system may store parity information associated with data in one or more latches associated with one or more planes before writing the data from the latches to the one or more planes. The parity information may be transferred from the latches to the one or more planes. The memory system may temporarily transfer the parity information from the latches to the planes before completing the write operation in response to initiating a write operation that uses more of the latches, and may transfer the parity information back to the latches after the write operation is completed. The memory system may store, retrieve, and transfer the parity information to or from the latches according to an interleaving scheme associated with different write operations of the memory system.

Abstract: Methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. A memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. The memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.

Abstract: Methods, systems, and devices for error correction configurations for memory systems are described. The described techniques provide for a memory system to evaluate one or more additional conditions when determining whether to initiate a refresh operation. For example, the memory system may determine whether the bit error rate (BER) of a page of memory cells satisfies a lower bound threshold corresponding to the BER threshold that triggers a refresh operation, and an upper bound threshold indicative of a BER at which a refresh operation may be prioritized. If the BER of a page is within the range of threshold values, the memory system may generate one or more additional layers of encoding associated with the page and may postpone the refresh operation for a duration.

Abstract: Methods, systems, and devices for synchronizing operations between decks of a memory system are described. In some examples, a memory system may determine a PEC difference between sister decks of physical blocks of the memory system. A memory system controller may associate the sister decks with respective virtual blocks. The controller may scan each virtual block of the memory system to determine which blocks are to be recycled, and may generate a list of virtual blocks having a VPC that satisfies a first threshold. In some cases, the controller may perform one or more threshold comparisons to determine whether to perform the maintenance operation on the first sister deck or both the first sister deck and the second sister deck.

Abstract: Methods, systems, and devices for access operations on weak word lines are described. A memory system may receive a command and may determine that the command is associated with a word line having a characteristic that satisfies a threshold value. If the command is a first type, such as a programming command (e.g., a write command), the memory system may perform the programming command using a first type of write operation (of a plurality of types of write operations). If the command is a second type, such as a read operation, the memory system may perform the read operation using a first type of read operation (of a plurality of types of read operations).

Abstract: Methods, systems, and devices for word line voltage management for a memory system are described. A memory system may determine a minimum threshold voltage for writing to a block of pages of a memory die, store an indication of the minimum threshold voltage in a first register of the memory die, and transfer the indication of the minimum threshold voltage directly from the first register to a second register of the memory die in response to receiving a first command from a controller. The controller may refrain from transmitting a second command prior to a subsequent write command, where the write command may include one or more additional bits indicating that the memory system is to use the minimum threshold voltage to write data to one or more pages of the block.

Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

Abstract: Methods, systems, and devices for garbage collection based on data characteristics are described. A memory system may receive a write command associated with a first logical block address (LBA) of a virtual block of the memory system, where the virtual block may be associated with a first value indicating a version of the virtual block. The memory system may adjust a value of a first counter within a mapping table in response to a difference between the first value and a second value satisfying a first threshold value. The second value may indicate a quantity of opened virtual blocks. The memory system may determine whether the value of the first counter satisfies a second threshold value, and transfer as part of garbage collection, data associated with the virtual block to a second virtual block in response to the value of the first counter satisfying the second threshold value.

Abstract: Methods, systems, and devices for techniques for transferring data between memory devices are described. A memory system may pre-fetch one or more subsets of data associated with the data transfer operation from a first die of the memory system and a second die of the memory system prior to initiating a programming operation on either die. For example, to perform a data folding operation for a set of data which includes a first subset of data stored to the first die and a second subset of data stored to the second die, the memory system may retrieve both the first subset from the first die and the second subset from the second die prior to performing a programming operation on either die.

Abstract: Methods, systems, and devices for techniques for improved data folding are described. A memory system may perform a two-pass data transfer operation to transfer data from a source block to a destination block that includes temporarily storing the data in a buffer as part of a first pass and bypassing the buffer during a second pass. The memory system may store information associated with the first portion, such as whether an error was detected in the data, a time associated with the first portion, and a temperature of the source block. The memory system may determine whether one or more conditions associated with the information are satisfied. If the conditions are satisfied, the memory system may perform the second portion by issuing a command to transfer the data from the source block to the destination block without passing through the buffer, such as a copyback command.

Abstract: Methods, systems, and devices for concurrent maintenance and write operations are described. In some instances, a memory system may be performing a maintenance operation (e.g., a folding operation) and a write command may be received (e.g., from a host system). The memory system may suspend the maintenance operation and may write data associated with the write command using a first type of write operation (e.g., a single-pass write operation). After writing the data, the memory system may resume the maintenance operation. If an error control operation had been previously performed on data associated with the suspended (and subsequently resumed) maintenance operation, the associated data may be written using a second type of write operation (e.g., a two-pass write operation).