Abstract: Methods, systems, and devices for resuming write operation after suspension are described. A memory system may be configured to determine an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determine a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resume the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.

Abstract: A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.

Abstract: A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction codes. Once scanned, a range of pages within the plurality of memory devices with uncorrectable error correction codes associated with a write abort error may be determined. The stage of multi-pass programming achieved on each page within that range is then established. Once calculated, the previously aborted multi-pass programming of each page within the range of pages can continue until completion. Upon completion, normal operations may continue without discarding physical data location.

Abstract: Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.

Abstract: A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.

Abstract: Storage devices may be configured to desirably reduce the time required to perform a physical secure erase operation. The storage device includes a controller that is configured to direct the storage device to receive a physical secure erase command. The storage device can then identify the one or more blocks within the memory array for secure erasure based on the received physical secure erase command. For each block identified for erasure, the storage device further evaluates the block to determine the level type of cells within the block. In response to the cell level type being single-level, a single-cell erase command is issued to perform a single-level cell erase on the block. Conversely, in response to the cell level type being a higher-dimensional cell, a modified single-cell erase command to perform a modified single-level cell erase on the block is issued.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.

Abstract: A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the plurality of memory cells. The second programming phase includes maintaining a margin of separation between two adjacent voltage distributions of the second set of voltage distributions after each of the second plurality of program pulses. This scheme achieves better margin using an aggressive quick pass approach, which helps with data recovery in case of power loss events.

Abstract: A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.

Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.

Abstract: A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.

Abstract: Storage devices may be configured to desirably reduce the time required to perform a physical secure erase operation. The storage device includes a controller that is configured to direct the storage device to receive a physical secure erase command. The storage device can then identify the one or more blocks within the memory array for secure erasure based on the received physical secure erase command. For each block identified for erasure, the storage device further evaluates the block to determine the level type of cells within the block. In response to the cell level type being single-level, a single-cell erase command is issued to perform a single-level cell erase on the block. Conversely, in response to the cell level type being a higher-dimensional cell, a modified single-cell erase command to perform a modified single-level cell erase on the block is issued.

Abstract: Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.