Abstract: Aspects of a storage device including a memory and a controller are provided which allow for efficient programming of cells on word lines using different scrambling seeds. The controller attempts to program cells of the memory by applying data scrambled using a first scrambling seed to the word line. If this attempt to program fails, the controller scrambles the data using a second, different scrambling seed and attempts to program the cells by applying the re-scrambled data to the word line. If this re-attempt also fails, the word line is listed. Then when the controller receives other data, the controller performs a final programming attempt with the other data scrambled using the second scrambling seed. If this further attempt fails, the controller identifies the block including the failed word line as a GBB. Thus, fewer GBBs may be incorrectly identified, reducing DPPM and improving memory yield of the storage device.

Abstract: A storage device may detect errors during data transfer. Upon detection of one or more data transfer errors, for example, the storage device can begin to scan pages within a plurality of memory devices for uncorrectable error correction codes. Once scanned, a range of pages within the plurality of memory devices with uncorrectable error correction codes associated with a write abort error may be determined. The stage of multi-pass programming achieved on each page within that range is then established. Once calculated, the previously aborted multi-pass programming of each page within the range of pages can continue until completion. Upon completion, normal operations may continue without discarding physical data location.

Abstract: Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for efficient programming of cells on word lines using different scrambling seeds. The controller attempts to program cells of the memory by applying data scrambled using a first scrambling seed to the word line. If this attempt to program fails, the controller scrambles the data using a second, different scrambling seed and attempts to program the cells by applying the re-scrambled data to the word line. If this re-attempt also fails, the word line is listed. Then when the controller receives other data, the controller performs a final programming attempt with the other data scrambled using the second scrambling seed. If this further attempt fails, the controller identifies the block including the failed word line as a GBB. Thus, fewer GBBs may be incorrectly identified, reducing DPPM and improving memory yield of the storage device.

Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.

Abstract: A non-volatile storage apparatus includes a plurality of non-volatile memory cells and control circuitry. The control circuitry is configured to apply one or more soft erase pulses to the plurality of non-volatile memory cells to reduce threshold voltages of the plurality of non-volatile memory cells from initial levels corresponding to programmed data to intermediate levels below the initial levels and above an erased level. The control circuitry is configured to apply one or more soft programming pulse to increase threshold voltages of the plurality of non-volatile memory cells from the intermediate levels to final levels corresponding to the programmed data.