Patents by Inventor Amol Ramesh Joshi
Amol Ramesh Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830942Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: GrantFiled: March 4, 2021Date of Patent: November 28, 2023Assignee: Infineon Technologies LLCInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Publication number: 20220302297Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: ApplicationFiled: March 4, 2021Publication date: September 22, 2022Applicant: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 10944000Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: GrantFiled: December 3, 2019Date of Patent: March 9, 2021Assignee: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Publication number: 20200212215Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.Type: ApplicationFiled: December 3, 2019Publication date: July 2, 2020Applicant: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 10622370Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: September 25, 2015Date of Patent: April 14, 2020Assignee: Monterey Research, LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, Youseok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Ramesh Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 10516044Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.Type: GrantFiled: October 21, 2013Date of Patent: December 24, 2019Assignee: Cypress Semiconductor CorporationInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Publication number: 20140061771Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.Type: ApplicationFiled: November 11, 2013Publication date: March 6, 2014Applicants: Spansion, LLC., Advanced Micro Devices, Inc.Inventors: Meng Ding, Amol Ramesh Joshi, Lei Xue, Takashi Orimoto, Kuo-Tung Chang
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Publication number: 20140042514Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicants: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 8587049Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.Type: GrantFiled: July 17, 2006Date of Patent: November 19, 2013Assignees: Spansion, LLC, Advanced Micro Devices, Inc.Inventors: Meng Ding, Amol Ramesh Joshi, Lei Xue, Takashi Orimoto, Kuo-Tung Chang
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Patent number: 8564041Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.Type: GrantFiled: October 20, 2006Date of Patent: October 22, 2013Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Angela T. Hui, Wenmei Li, Minh Van Ngo, Amol Ramesh Joshi, Kuo-Tung Chang
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Patent number: 8143661Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.Type: GrantFiled: October 10, 2006Date of Patent: March 27, 2012Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Patent number: 7995386Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.Type: GrantFiled: November 21, 2008Date of Patent: August 9, 2011Assignee: Spansion LLCInventors: Yuji Mizuguchi, Mark W. Randolph, Darlene Gay Hamilton, Yi He, Zhizheng Liu, Yanxia (Emma) Lin, Xianmin Yi, Gulzar Kathawala, Amol Ramesh Joshi, Kuo-Tung Chang, Edward Franklin Runnion, Sung-Chul Lee, Sung-Yong Chung, Yanxiang Liu, Yu Sun
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Publication number: 20100128521Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: SPANSION LLCInventors: Yuji Mizuguchi, Mark W. Randolph, Darlene Gay Hamilton, Yi He, Zhizheng Liu, Yanxia (Emma) Lin, Xianmin Yi, Gulzar Kathawala, Amol Ramesh Joshi, Kuo-Tung Chang, Edward Franklin Runnion, Sung-Chul Lee, Sung-Yong Chung, Yanxiang Liu, Yu Sun
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Patent number: 7704878Abstract: A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.Type: GrantFiled: October 3, 2005Date of Patent: April 27, 2010Assignees: Advanced Micro Devices, Inc,, Spansion LLCInventors: Minh Van Ngo, Angela T. Hui, Amol Ramesh Joshi, Wenmei Li, Ning Cheng, Ankur Bhushan Agarwal, Norimitsu Takagi
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Patent number: 7705390Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.Type: GrantFiled: March 24, 2008Date of Patent: April 27, 2010Assignee: Spansion LLCInventors: Amol Ramesh Joshi, Ning Cheng, Minghao Shen
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Patent number: 7675104Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.Type: GrantFiled: July 31, 2006Date of Patent: March 9, 2010Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Amol Ramesh Joshi, Harpreet Sachar, YouSeok Suh, Shenqing Fang, Chih-Yuh Yang, Lovejeet Singh, David H. Matsumoto, Hidehiko Shiraiwa, Kuo-Tung Chang, Scott A. Bell, Allison Holbrook, Satoshi Torii
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Publication number: 20080169502Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.Type: ApplicationFiled: March 24, 2008Publication date: July 17, 2008Inventors: Amol Ramesh Joshi, Ning Cheng, Minghao Shen
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Publication number: 20080150011Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Simon Siu-Sing Chan, Lei Xue, YouSeok Suh, Amol Ramesh Joshi, Hidehiko Shiraiwa, Harpreet Sachar, Kuo-Tung Chang, Connie Pin Chin Wang, Paul R. Besser, Shenqing Fang, Meng Ding, Takashi Orimoto, Wei Zheng, Fred TK Cheung
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Publication number: 20080150000Abstract: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: SPANSION LLCInventors: YouSeok Suh, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, Shenqing Fang
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Publication number: 20080142874Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.Type: ApplicationFiled: December 16, 2006Publication date: June 19, 2008Applicants: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Hidehiko Shiraiwa, Takayuki Maruyama, Kuo-Tung Chang, YouSeok Suh, Amol Ramesh Joshi, Harpreet Sachar, Simon Siu-Sing Chan