Patents by Inventor Amr Fahim
Amr Fahim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9971378Abstract: A clock phase detector circuit device and method. The device can include a first and second clock inputs connected to two pairs of transistors, each transistor having a first, second, and third terminal. The first pair includes a p-type transistor and n-type transistor configured such that the third terminals of each transistor are connected to form a first output node. Similarly, the second pair includes a p-type transistor and n-type transistor, the second p-type transistor and n-type transistor configured such that the third terminals of each transistor are connected to form a second output node. The first clock input is connected to the first terminals of the first p-type transistor and the second n-type transistor, while the second clock input is connected to the first terminals of the second p-type transistor and the first n-type transistor. As configured, the voltage outputs represent the phase difference between the clock inputs.Type: GrantFiled: July 25, 2017Date of Patent: May 15, 2018Assignee: INPHI CORPORATIONInventor: Amr Fahim
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Patent number: 8005449Abstract: A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.Type: GrantFiled: June 11, 2008Date of Patent: August 23, 2011Assignee: Newport Media, Inc.Inventors: Edward Youssoufian, Amr Fahim
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Patent number: 7973861Abstract: A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.Type: GrantFiled: April 19, 2007Date of Patent: July 5, 2011Assignee: Newport Media, Inc.Inventors: Mohy Abdelgany, Frank Carr, Hassan Elwan, Amr Fahim, Edward Youssoufian
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Publication number: 20090311985Abstract: A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.Type: ApplicationFiled: June 11, 2008Publication date: December 17, 2009Applicant: NEWPORT MEDIA, INC.Inventors: Edward Youssoufian, Amr Fahim
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Patent number: 7592863Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.Type: GrantFiled: May 30, 2007Date of Patent: September 22, 2009Assignee: Newport Media, Inc.Inventors: Hassan Elwan, Amr Fahim, Edward Youssounan, Ahmed A. Emira, Dejun Wang
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Patent number: 7583555Abstract: A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage.Type: GrantFiled: March 30, 2004Date of Patent: September 1, 2009Assignee: QUALCOMM IncorporatedInventors: Inyup Kang, Karthikeyan Ethirajan, Matthew Levi Severson, Mohamed Elgebaly, Manoj Sachdev, Amr Fahim
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Patent number: 7525372Abstract: A low noise nth order filter, system, and method includes a plurality of nested general immittance converters (GICs) operatively connected to one another in successive GIC stages; and a capacitor operatively connected to each of the GICs, wherein a first successive GIC stage begins at a first node located in between a previous GIC stage and a corresponding capacitor operatively connected to the previous GIC stage. A second successive GIC stage begins at a second node located in between the first node and the first successive GIC stage. The filter may further comprise a resistor operatively connected to at least one successive GIC stage, wherein the resistor is preferably located in between the first node and the first successive GIC stage.Type: GrantFiled: March 8, 2007Date of Patent: April 28, 2009Assignee: Newport Media, Inc.Inventors: Hassan Elwan, Amr Fahim, Aly Ismail, Edward Youssoufian
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Publication number: 20080297239Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Inventors: Hassan Elwan, Amr Fahim, Edward Youssounan, Ahmed A. Emira, Dejun Wang
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Publication number: 20080259219Abstract: A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.Type: ApplicationFiled: April 19, 2007Publication date: October 23, 2008Inventors: Mohy Abdelgany, Frank Carr, Hassan Elwan, Amr Fahim, Edward Youssoufian
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Publication number: 20080220737Abstract: A low noise nth order filter, system, and method includes a plurality of nested general immittance converters (GICs) operatively connected to one another in successive GIC stages; and a capacitor operatively connected to each of the GICs, wherein a first successive GIC stage begins at a first node located in between a previous GIC stage and a corresponding capacitor operatively connected to the previous GIC stage. A second successive GIC stage begins at a second node located in between the first node and the first successive GIC stage. The filter may further comprise a resistor operatively connected to at least one successive GIC stage, wherein the resistor is preferably located in between the first node and the first successive GIC stage.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Hassan Elwan, Amr Fahim, Aly Ismail, Edward Youssoufian
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Patent number: 7365607Abstract: A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.Type: GrantFiled: August 10, 2006Date of Patent: April 29, 2008Assignee: Newport Media, Inc.Inventor: Amr Fahim
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Patent number: 7352238Abstract: A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.Type: GrantFiled: June 21, 2006Date of Patent: April 1, 2008Assignee: Newport Media, Inc.Inventors: Hassan Elwan, Amr Fahim, Aly Ismail, Edward Youssoufian
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Patent number: 7348839Abstract: A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.Type: GrantFiled: August 23, 2006Date of Patent: March 25, 2008Assignee: Newport Media, Inc.Inventors: Amr Fahim, Hassan Elwan, Aly Ismail
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Publication number: 20080048791Abstract: A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.Type: ApplicationFiled: August 10, 2006Publication date: February 28, 2008Inventor: Amr Fahim
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Publication number: 20080048773Abstract: A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Inventors: Amr Fahim, Hassan Elwan, Aly Ismail
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Publication number: 20070296490Abstract: A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.Type: ApplicationFiled: June 21, 2006Publication date: December 27, 2007Applicant: Newport Media, Inc.Inventors: Hassan Elwan, Amr Fahim, Aly Ismail, Edward Youssoufian
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Publication number: 20060226916Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.Type: ApplicationFiled: April 11, 2005Publication date: October 12, 2006Inventors: Octavian Florescu, Amr Fahim, Chiewcharn Narathong
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Patent number: 7119606Abstract: An N-FET headswitch has improved performance (e.g., less leakage current, lower ON resistance, and smaller area) over a conventional P-FET headswitch. The N-FET headswitch includes at least one N-FET device and couples between a power supply and a load circuit, which may be, e.g., a microprocessor, a digital signal processor, or a memory unit. The headswitch couples the power supply to the load circuit when the headswitch is enabled and cuts off the power supply from the load circuit when disabled. A charge pump couples to the headswitch and provides a control signal. This control signal is sufficiently high when the headswitch is enabled to ensure that the N-FET device operates in a linear region and has a small drain to source voltage drop. The headswitch may be operated as a power switch or in a feedback configuration to implement a linear or a digital voltage regulator.Type: GrantFiled: July 10, 2003Date of Patent: October 10, 2006Assignee: QUALCOMM, IncorporatedInventor: Amr Fahim
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Patent number: 7042972Abstract: A digital PLL includes an adaptive PFD, an adaptive loop filter, an iDAC, an ICO, and a divider. The adaptive PFD receives a reference signal and a feedback signal, determines phase error between the two signals, and provides a PFD value for each phase comparison period. The magnitude of the PFD value is adjusted to achieve fast frequency acquisition and reduced jitter. The adaptive loop filter updates its output whenever a PFD value is received, widens the PLL loop bandwidth if a large phase error is detected, and narrows the loop bandwidth if a small average phase error is detected. The iDAC, which can be implemented with both steered and single-ended current sources, converts the loop filter output into analog current. The ICO provides an oscillator signal having a phase determined by the iDAC output. The divider divides the oscillator signal by a factor of N and provides the feedback signal.Type: GrantFiled: August 19, 2003Date of Patent: May 9, 2006Assignee: Qualcomm IncInventor: Amr Fahim
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Patent number: RE44551Abstract: A tuner for use in mobile television devices comprises at least one RF front end component comprising a LNA adapted to amplify mobile television signals; a PLL circuit to generate signals; and a pair of mixers to receive the signals from the LNA and the PLL circuit and downconvert the signals; an analog baseband component connected to the RF front end component, wherein the analog baseband component comprises I and Q channel signal paths each comprising a tunable high order impedance filter; at least one signal amplification stage; and a signal filter stage connected to the signal amplification stage, wherein the analog baseband component further comprises a plurality of switches operatively connected to the I and Q channel signal paths, and wherein the plurality of switches are selectively opened and closed in multiple configurations in order to allow the tuner to receive mobile TV signals for all mobile TV standards.Type: GrantFiled: October 4, 2012Date of Patent: October 22, 2013Assignee: Newport Media, Inc.Inventors: Mohy Abdelgany, Frank Carr, Hassan Elwan, Amr Fahim, Edward Youssoufian