Abstract: An MN counter with analog interpolation (“MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

Abstract: An MN counter with analog interpolation (an “MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

Abstract: An N-FET headswitch has improved performance (e.g., less leakage current, lower ON resistance, and smaller area) over a conventional P-FET headswitch. The N-FET headswitch includes at least one N-FET device and couples between a power supply and a load circuit, which may be, e.g., a microprocessor, a digital signal processor, or a memory unit. The headswitch couples the power supply to the load circuit when the headswitch is enabled and cuts off the power supply from the load circuit when disabled. A charge pump couples to the headswitch and provides a control signal. This control signal is sufficiently high when the headswitch is enabled to ensure that the N-FET device operates in a linear region and has a small drain to source voltage drop. The headswitch may be operated as a power switch or in a feedback configuration to implement a linear or a digital voltage regulator.

Abstract: This disclosure is directed to a frequency synthesizer for use in a wireless communication device. The frequency synthesizer includes an oscillator, such as a voltage controlled oscillator (VCO) and a &Sgr;&Dgr;-controlled phase-locked loop (PLL) that determines and controls the of the output frequency of the frequency synthesizer. The &Sgr;&Dgr;-controlled PLL may implement a dithering signal generation technique that can reduce or eliminate the introduction of an average frequency offset.

Abstract: A digital PLL includes an adaptive PFD, an adaptive loop filter, an iDAC, an ICO, and a divider. The adaptive PFD receives a reference signal and a feedback signal, determines phase error between the two signals, and provides a PFD value for each phase comparison period. The magnitude of the PFD value is adjusted to achieve fast frequency acquisition and reduced jitter. The adaptive loop filter updates its output whenever a PFD value is received, widens the PLL loop bandwidth if a large phase error is detected, and narrows the loop bandwidth if a small average phase error is detected. The iDAC, which can be implemented with both steered and single-ended current sources, converts the loop filter output into analog current. The ICO provides an oscillator signal having a phase determined by the iDAC output. The divider divides the oscillator signal by a factor of N and provides the feedback signal.

Abstract: This disclosure is directed to a frequency synthesizer for use in a wireless communication device. The frequency synthesizer includes an oscillator, such as a voltage controlled oscillator (VCO) and a &Sgr;&Dgr;-controlled phase-locked loop (PLL) that determines and controls the of the output frequency of the frequency synthesizer. The &Sgr;&Dgr;-controlled PLL may implement a dithering signal generation technique that can reduce or eliminate the introduction of an average frequency offset.