Patents by Inventor Amram Eitan

Amram Eitan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128152
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20240047408
    Abstract: An embodiment semiconductor device may include an electrical interconnect layer, a bonding pad electrically coupled to the electrical interconnect layer, a stacked film structure including a first film partially covering a surface of the bonding pad and a second film partially covering the first film, a first aperture formed in the first film over a portion of the surface of the bonding pad, a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture, and a solder material portion formed in contact with the bonding pad. The solder material portion may include a first width that is less than a size of the second aperture such that the solder material portion does not contact the second film.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Amram Eitan, Wen-Yi Lin, Teng-Yuan Lo
  • Publication number: 20240021493
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20240014097
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Patent number: 11676900
    Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Nitin Deshpande, Shawna M. Liff, Omkar Karhade, Amram Eitan, Timothy A. Gosselin
  • Publication number: 20230095281
    Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Kyle McElhinny, Hongxia Feng, Xiaoying Guo, Steve Cho, Jung Kyu Han, Changhua Liu, Leonel Arana, Rahul Manepalli, Dingying Xu, Amram Eitan
  • Patent number: 11075166
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Publication number: 20210066155
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Elizabeth NOFEN, Shripad GOKHALE, Nick ROSS, Amram EITAN, Nisha ANANTHAKRISHNAN, Robert M. NICKERSON, Purushotham Kaushik MUTHUR SRINATH, Yang GUO, John C. DECKER, Hsin-Yu LI
  • Publication number: 20200395301
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Eric J. LI, Timothy A. GOSSELIN, Yoshihiro TOMITA, Shawna M. LIFF, Amram EITAN, Mark SALTAS
  • Patent number: 10790231
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Publication number: 20190355666
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Application
    Filed: July 12, 2019
    Publication date: November 21, 2019
    Applicant: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Patent number: 10475715
    Abstract: Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Venmathy McMahan, Sivakumar Nagarajan, Elah Bozorg-Grayeli, Amrita Mallik, Kuang-Han Chu, Liwei Wang, Nisha Ananthakrishnan, Craig J. Weinman, Amram Eitan
  • Patent number: 10418329
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Publication number: 20190206821
    Abstract: Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Huxiao XIE, Amram EITAN, Xiao LU
  • Publication number: 20190202136
    Abstract: Apparatuses, systems and methods associated with procedures and adhesive elements for affixing components together are disclosed herein. In embodiments, an assembly may include a first component and a second component coupled to the first component. The assembly may further include a plurality of adhesive elements located between the first component and the second component, wherein the plurality of adhesive elements couple the second component to the first component, and wherein each adhesive element of the plurality of adhesive elements is equidistance from adjacent adhesive elements of the plurality of adhesive elements. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Taylor GAINES, Mark SALTAS, Amram EITAN
  • Publication number: 20190099777
    Abstract: A fluid applicator configured to apply a fluid to at least one substrate feature includes a manifold plate having an inflow orifice and a manifold reservoir. A distributor plate is coupled with the manifold plate. The distributor plate includes a distributor surface extending across the manifold reservoir, and a distributor port array spread across the distributor surface and in communication with the manifold reservoir. A compressible reticulated media is configured for applying the fluid to the at least one substrate feature. The compressible reticulated media includes an input interface coupled along the distributor surface, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the substrate interface.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Ken P. Hackenberg, Nachiket R. Raravikar, James C. Matayabas, JR., Elizabeth Nofen, Seth B. Reynolds, Amram Eitan, Nisha Ananthakrishnan
  • Publication number: 20180358296
    Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.
    Type: Application
    Filed: December 22, 2015
    Publication date: December 13, 2018
    Inventors: Eric J. LI, Nitin DESHPANDE, Shawna M. LIFF, Omkar KARHADE, Amram EITAN, Timothy A. GOSSELIN
  • Publication number: 20180337129
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Application
    Filed: December 11, 2015
    Publication date: November 22, 2018
    Applicant: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Patent number: 9786517
    Abstract: Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Lars D. Skoglund, Anil R. Indluru, Edward R. Prack, Danish Faruqui, Tyler N. Osborn, Amram Eitan, Timothy A. Gosselin
  • Patent number: 9748199
    Abstract: Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are disclosed. In some embodiments, the cooling manifold comprises a pre-mixing chamber that is separated from a mixing chamber by a baffle. The baffle may comprise at least one concentric pattern formed through the baffle such that the primary cooling fluid in the pre-mixing chamber is substantially evenly distributed to the mixing chamber. The pre-mixing chamber may be coupled to a source of primary cooling fluid. The mixing chamber may have an input configured to accept the primary cooling fluid and an output to output the primary cooling fluid.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Hemanth Dhavaleswarapu, Zhihua Li, Joseph Petrini, Steven B. Roach, Shankar Devasenathipathy, George Kostiew, Amram Eitan