Patents by Inventor Amram Eitan
Amram Eitan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170170088Abstract: Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.Type: ApplicationFiled: June 17, 2015Publication date: June 15, 2017Inventors: Venmathy McMahan, Sivakumar Nagarajan, Elah Bozorg-Grayeli, Amrita Mallik, Kuang-Han Chu, Liwei Wang, Nisha Ananthakrishnan, Craig J. Weinman, Amram Eitan
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Publication number: 20170154828Abstract: A method and machine-readable medium including non-transitory program instructions that when executed by a processor cause the processor to perform a method including measuring at least one parameter of a substrate or a die; and establishing or modifying a thermal compression bonding recipe based on the at least one parameter, wherein the thermal compression bonding recipe is operable for thermal compression bonding of the die and the substrate. A thermal compression bonding tool including a pedestal operable to hold a substrate during a thermal compression bonding process and a bond head operable to engage a die, the tool including a controller machine readable instructions to process a substrate and a die combination, the instructions including an algorithm to implement or modify a thermal compression bonding process based on a parameter of a substrate or die.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Inventors: Timothy A. GOSSELIN, Patrick NARDI, Kartik SRINIVASAN, Amram EITAN, Ji Yong PARK, Christopher L. RUMER, George S. KOSTIEW
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Patent number: 9653411Abstract: An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the electronic component by melting the metal powder onto the electronic component. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; and a porous coating that includes grains of metal powder formed onto the substrate by melting the metal powder onto the substrate. An electronic package that includes a substrate; an electronic component mounted to a surface of the substrate; an initial mold covering the electronic component; and a porous coating that includes grains of metal powder formed onto the initial mold by melting the metal powder onto the initial mold.Type: GrantFiled: December 18, 2015Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Donglai David Lu, Zhaozhi George Li, Matthew T. Magnavita, Amram Eitan, Peng Chen
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Publication number: 20160211238Abstract: Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are disclosed. In some embodiments, the cooling manifold comprises a pre-mixing chamber that is separated from a mixing chamber by a baffle. The baffle may comprise at least one concentric pattern formed through the baffle such that the primary cooling fluid in the pre-mixing chamber is substantially evenly distributed to the mixing chamber. The pre-mixing chamber may be coupled to a source of primary cooling fluid. The mixing chamber may have an input configured to accept the primary cooling fluid and an output to output the primary cooling fluid.Type: ApplicationFiled: March 7, 2016Publication date: July 21, 2016Inventors: Hemanth Dhavaleswarapu, Zhihua Li, Joseph Petrini, Steven B. Roach, Shankar Devasenathipathy, George S. Kostiew, Amram Eitan
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Patent number: 9282650Abstract: Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are disclosed. In some embodiments, the cooling manifold comprises a pre-mixing chamber that is separated from a mixing chamber by a baffle. The baffle may comprise at least one concentric pattern formed through the baffle such that the primary cooling fluid in the pre-mixing chamber is substantially evenly distributed to the mixing chamber. The pre-mixing chamber may be coupled to a source of primary cooling fluid. The mixing chamber may have an input configured to accept the primary cooling fluid and an output to output the primary cooling fluid.Type: GrantFiled: December 18, 2013Date of Patent: March 8, 2016Assignee: Intel CorporationInventors: Hemanth Dhavaleswarapu, Zhihua Li, Joseph Petrini, Steven B. Roach, Shankar Devasenathipathy, George Kostiew, Amram Eitan
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Publication number: 20150173209Abstract: Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are disclosed. In some embodiments, the cooling manifold comprises a pre-mixing chamber that is separated from a mixing chamber by a baffle. The baffle may comprise at least one concentric pattern formed through the baffle such that the primary cooling fluid in the pre-mixing chamber is substantially evenly distributed to the mixing chamber. The pre-mixing chamber may be coupled to a source of primary cooling fluid. The mixing chamber may have an input configured to accept the primary cooling fluid and an output to output the primary cooling fluid.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: Hemanth Dhavaleswarapu, Zhihua Li, Joseph Petrini, Steven B. Roach, Shankar Devasenathipathy, George Kostiew, Amram Eitan
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Publication number: 20150072479Abstract: Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material.Type: ApplicationFiled: September 9, 2013Publication date: March 12, 2015Inventors: Rajendra C. Dias, Lars D. Skoglund, Anil R. Indluru, Edward R. Prack, Danish Faruqui, Tyler N. Osborn, Amram Eitan, Timothy A. Gosselin
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Patent number: 7851342Abstract: The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed.Type: GrantFiled: March 30, 2007Date of Patent: December 14, 2010Assignee: Intel CorporationInventors: Dingying Xu, Amram Eitan
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Patent number: 7727814Abstract: A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.Type: GrantFiled: July 10, 2008Date of Patent: June 1, 2010Assignee: Intel CorporationInventors: Daewoong Suh, Amram Eitan, Yongki Min
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Publication number: 20090294515Abstract: A poly(alkylene carbonate) tack agent may be used to secure an electrical component, such as an integrated circuit, to a substrate for soldering. The tack agent may disintegrate or vaporize at normal reflow temperatures so that no clean up is needed. In some embodiments, flexless soldering may be implemented. If flux is desired, the flux may be mixed with the tack agent in some embodiments. For example, the flux may be incorporated in microcapsules within the tack agent.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Edward R. Prack, Amram Eitan
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Patent number: 7557036Abstract: A method, system, and apparatus, the method including, in some embodiments, applying a via filling material in a film format and at a first temperature to a backside of a silicon wafer having a plurality of vias therein, heating the via filling material to a second temperature to cause the via filling material to flow into and fill the plurality of vias, and applying a die attach material over the plurality of vias filled with the via filling material.Type: GrantFiled: March 30, 2006Date of Patent: July 7, 2009Assignee: Intel CorporationInventors: Amram Eitan, Dingying Xu
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Publication number: 20080242079Abstract: The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Dingying Xu, Amram Eitan
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Patent number: 7402909Abstract: A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.Type: GrantFiled: April 28, 2005Date of Patent: July 22, 2008Assignee: Intel CorporationInventors: Daewoong Suh, Amram Eitan, Yongki Min
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Publication number: 20070298525Abstract: Stress in microelectronic integrated circuit packages may be measured in situ using carbon nanotube networks. An array of carbon nanotubes strung between upstanding structures may be used to measure the local stress in two dimensions. Because of the characteristics of the carbon nanotubes, a highly accurate stress measurement may be achieved. In some cases, the carbon nanotubes and the upstanding structures may be secured to a substrate that is subsequently attached within a microelectronic package. In other cases, the nanotube structures may be formed directly onto integrated circuit dice.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Inventors: Nachiket R. Raravikar, Amram Eitan, Neha Patel
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Publication number: 20070235840Abstract: A method, system, and apparatus, the method including, in some embodiments, applying a via filling material in a film format and at a first temperature to a backside of a silicon wafer having a plurality of vias therein, heating the via filling material to a second temperature to cause the via filling material to flow into and fill the plurality of vias, and applying a die attach material over the plurality of vias filled with the via filling material.Type: ApplicationFiled: March 30, 2006Publication date: October 11, 2007Inventors: Amram Eitan, Dingying Xu
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Publication number: 20070152314Abstract: A stacked die package comprises a first die on a substrate, a die attach layer superjacent to the first die, and a second die on the die attach layer. The die attach layer comprises a die attach material having a glass transition temperature substantially in the range of 150-180° C. Raising the glass transition temperature reduces the mismatch in the coefficients of thermal expansion (CTE) between the die attach and the mold compound that surrounds the first die in the package.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventors: Rahul Manepalli, Amram Eitan, Prasanna Raghavan
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Publication number: 20060243958Abstract: A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.Type: ApplicationFiled: April 28, 2005Publication date: November 2, 2006Applicant: Intel CorporationInventors: Daewoong Suh, Amram Eitan, Yongki Min