Patents by Inventor Amrit P. Singh
Amrit P. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220309118Abstract: A system is described that includes an electronic program guide (EPG) data receiver and a media content catalog enhancer. The EPG receiver is configured to receive EPG data from an EPG data provider. The media content catalog enhancer is configured to determine that an item of media content identified by the EPG data comprises new media content and, in response to determining that the item of media content identified by the EPG data comprises new media content, to cause a web crawler to crawl a source website associated with the new media content to obtain information about the new media content and to store the obtained information about the new media content in a database, the database comprising a catalog of media content that is searchable by an end user to identify and access content for playback via an end user device.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Amrit P. Singh, Sravan K. Andavarapu, Vinod K. Gopinath, Ashish D. Aggarwal
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Patent number: 11068526Abstract: Methods, systems, and computer program products are provided for obtaining enhanced metadata for media content searches. In one embodiment, computer program logic embodies a metadata receiver and a media content metadata matcher and combiner. The metadata receiver receives program metadata for a plurality of programs from a plurality of metadata sources. The media content metadata matcher and combiner is configured to perform a matching process whereby metadata associated with each of the plurality of programs is compared to metadata of each of the other plurality of programs to determine if the compared programs are the same program and if so, to combine the metadata from each program into a single program including enhanced metadata and store such in a database. A subsequent search for a program corresponding to the stored program returns at least some of the metadata associated with the program, and that enables accessing the program.Type: GrantFiled: January 25, 2019Date of Patent: July 20, 2021Assignee: Caavo IncInventors: Amrit P. Singh, Sravan K. Andavarapu, Jayanth Manklu, Anu Godara, Vinu Joseph, Vinod K. Gopinath, Ashish D. Aggarwal
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Patent number: 10917671Abstract: Methods, systems, and apparatuses are described herein for enhancing metadata of a recorded items of media content stored on a digital video recorder (DVR) associated with an end user. First metadata associated with the recorded item is determined from the DVR. An aired instance of the first media content is determined in program data from an electronic program guide that corresponds to the recorded item. Second metadata associated with the first media content is retrieved from at least one data source based at least on the identifying information. The first metadata and the second metadata are stored in an end user database in association with the end user.Type: GrantFiled: January 25, 2019Date of Patent: February 9, 2021Assignee: Caavo IncInventors: Amrit P. Singh, Sravan K. Andavarapu, Vinod K. Gopinath, Ashish D. Aggarwal
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Publication number: 20190238901Abstract: Methods, systems, and apparatuses are described herein for enhancing metadata of a recorded items of media content stored on a digital video recorder (DVR) associated with an end user. First metadata associated with the recorded item is determined from the DVR. An aired instance of the first media content is determined in program data from an electronic program guide that corresponds to the recorded item. Second metadata associated with the first media content is retrieved from at least one data source based at least on the identifying information. The first metadata and the second metadata are stored in an end user database in association with the end user.Type: ApplicationFiled: January 25, 2019Publication date: August 1, 2019Inventors: Amrit P. Singh, Sravan K. Andavarapu, Vinod K. Gopinath, Ashish D. Aggarwal
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Publication number: 20190236093Abstract: Embodiments are described herein for enabling fast and efficient media content searches across a wide variety of content providers using a graph database. For instance, metadata may be collected from different metadata sources. A graph database is generated that stores and organizes the metadata based on attributes of the metadata and the relationships therebetween. For example, each attribute is assigned to a node of the graph database. The nodes may be connected via an edge that represents a relationship between the nodes. Attributes of metadata retrieved from a first metadata source are associated with attributes of metadata retrieved from a second metadata source. When receiving a query, the graph database is traversed for media content items to recommend to a user. The media content items recommended to the user include items from different content providers that are determined based on the traversal of the nodes of the graph database.Type: ApplicationFiled: January 25, 2019Publication date: August 1, 2019Inventors: Sravan K. Andavarapu, Amrit P. Singh, Vinod K. Gopinath, Ashish D. Aggarwal
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Publication number: 20190236090Abstract: Methods, systems, and computer program products are provided for obtaining enhanced metadata for media content searches. In one embodiment, computer program logic embodies a metadata receiver and a media content metadata matcher and combiner. The metadata receiver receives program metadata for a plurality of programs from a plurality of metadata sources. The media content metadata matcher and combiner is configured to perform a matching process whereby metadata associated with each of the plurality of programs is compared to metadata of each of the other plurality of programs to determine if the compared programs are the same program and if so, to combine the metadata from each program into a single program including enhanced metadata and store such in a database. A subsequent search for a program corresponding to the stored program returns at least some of the metadata associated with the program, and that enables accessing the program.Type: ApplicationFiled: January 25, 2019Publication date: August 1, 2019Inventors: Amrit P. Singh, Sravan K. Andavarapu, Jayanth Manklu, Anu Godara, Vinu Joseph, Vinod K. Gopinath, Ashish D. Aggarwal
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Patent number: 10070465Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.Type: GrantFiled: December 20, 2015Date of Patent: September 4, 2018Assignee: NXP USA, INC.Inventors: Girraj K. Agrawal, Arvind Kaushik, Vincent Martinez, Amrit P. Singh
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Patent number: 10045366Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.Type: GrantFiled: July 18, 2016Date of Patent: August 7, 2018Assignee: NXP USA, INC.Inventors: Somvir Dahiya, Arvind Kaushik, Aviel Livay, Amrit P. Singh
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Publication number: 20180189409Abstract: A system is described that includes an electronic program guide (EPG) data receiver and a media content catalog enhancer. The EPG receiver is configured to receive EPG data from an EPG data provider. The media content catalog enhancer is configured to determine that an item of media content identified by the EPG data comprises new media content and, in response to determining that the item of media content identified by the EPG data comprises new media content, to cause a web crawler to crawl a source website associated with the new media content to obtain information about the new media content and to store the obtained information about the new media content in a database, the database comprising a catalog of media content that is searchable by an end user to identify and access content for playback via an end user device.Type: ApplicationFiled: December 28, 2017Publication date: July 5, 2018Inventors: Amrit P. Singh, Sravan K. Andavarapu, Vinod K. Gopinath, Ashish D. Aggarwal
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Patent number: 9893714Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.Type: GrantFiled: September 1, 2015Date of Patent: February 13, 2018Assignee: NXP USA, INC.Inventors: Akshat Mittal, Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh
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Publication number: 20180020468Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Inventors: SOMVIR DAHIYA, ARVIND KAUSHIK, AVIEL LIVAY, AMRIT P. SINGH
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Patent number: 9785368Abstract: A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.Type: GrantFiled: July 24, 2016Date of Patent: October 10, 2017Assignee: NXP USA, INC.Inventors: Ritika Sharma, Somvir Dahiya, Arvind Kaushik, Amrit P. Singh
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Publication number: 20170181192Abstract: An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second transform circuit that multiplies the resulting signal by a complex Z-C sequence and performs an inverse Fourier transform (iFT) operation to transform the multiplied signal from the frequency domain to the time domain. A DSP performs a delay profile analysis operation on the signal resulting from the iFT operation.Type: ApplicationFiled: December 20, 2015Publication date: June 22, 2017Inventors: GIRRAJ K. AGRAWAL, ARVIND KAUSHIK, VINCENT MARTINEZ, AMRIT P. SINGH
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Patent number: 9665510Abstract: A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.Type: GrantFiled: December 22, 2014Date of Patent: May 30, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh, Akshat Mittal
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Publication number: 20170063346Abstract: A FIR filter includes segment cells, each of which is configurable as an interpolation filter, a decimation filter, a symmetric filter, or an asymmetric filter. Two or more of the segment cells are configurable to be cascaded to form an interpolation filter, a decimation filter, a symmetric filter, an asymmetric filter, a complex symmetric filter, or a complex asymmetric filter. The FIR filter includes registers corresponding to the segment cells for storing coefficient values of the corresponding segment cells. The FIR filter further includes control circuits corresponding to the segment cells for generating control signals.Type: ApplicationFiled: September 1, 2015Publication date: March 2, 2017Inventors: Akshat Mittal, ARVIND KAUSHIK, PETER Z. RASHEV, AMRIT P. SINGH
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Publication number: 20160179715Abstract: A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.Type: ApplicationFiled: December 22, 2014Publication date: June 23, 2016Inventors: Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh, Akshat Mittal
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Publication number: 20160182015Abstract: A fractional and integer ratio polyphase interpolation filter changes the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N. The clock rate required to evaluate the output signal is M/N.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Vinay Gupta, Arvind Kaushik, Akshat Mittal, Amrit P. Singh
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Patent number: 9231530Abstract: A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal.Type: GrantFiled: January 8, 2015Date of Patent: January 5, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh, Akshat Mittal
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Patent number: 9130628Abstract: A digital pre-distorter (DPD) for an RF transceiver system having multiple antennas includes a DPD controller, first and second address generators, stream select and antenna select muxes, first and second lookup tables (LUTs), first and second dynamic routing logic units, multipliers, an adder, and an accumulator. The DPD controller generates antenna select, stream select and stream routing signals indicative of selection of antennas, the first and second LUTs, and input signals. The DPD controller configures the DPD to share the multipliers and the first and second LUTs between multiple antennas by providing the antenna select signal to the antenna select mux, the stream select signal to the stream select mux, and the stream routing signals to the first and second dynamic routing logic units.Type: GrantFiled: December 24, 2014Date of Patent: September 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Akshat Mittal, Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh
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Patent number: 9088472Abstract: A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.Type: GrantFiled: January 8, 2015Date of Patent: July 21, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Nikhil Jain, Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh