Patents by Inventor Amrit P. Singh

Amrit P. Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9088472
    Abstract: A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: July 21, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Nikhil Jain, Arvind Kaushik, Peter Z. Rashev, Amrit P. Singh
  • Patent number: 8432960
    Abstract: A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: April 30, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Girraj K. Agrawal, Asif Iqbal, Akshat Mittal, Ankit Pal, Amrit P. Singh
  • Publication number: 20110228839
    Abstract: A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 22, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Girraj K. Agrawal, Asif Iqbal, Akshat Mittal, Ankit Pal, Amrit P. Singh
  • Publication number: 20110090973
    Abstract: A method for determining a symbol boundary of a data packet of a received signal, where the data packet includes a first training field, a guard interval, and a second training field. The received signal is sampled to obtain multiple samples. A first symbol boundary estimate is determined using one or more block auto-correlation values. Thereafter, a second symbol boundary estimate is determined based on the first symbol boundary estimate and using one or more cross-correlation values. The second symbol boundary estimate then is shifted using moving average auto-correlation values for the samples in the vicinity of the second symbol boundary estimate to obtain an accurate symbol boundary estimate.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 21, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Mridul Manohar Mishra, Amrit P. Singh, Anshoo Tandon
  • Patent number: 7404139
    Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohit K. Prasad, Nitin Vig, Arnab K. Mitra, Amrit P. Singh, Gaurav Davra
  • Patent number: 7231586
    Abstract: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code word polynomials, where d is the number of unique code word polynomials. The computed set of 2d-1 unique branch metrics is stored in a memory. Path metrics are then calculated, based on the stored set of 2d-1 unique branch metrics. A decoded data symbol sequence is generated based on the computed path metrics.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: June 12, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohit K. Prasad, Gaurav Davra, Arnab K. Mitra, Amrit P. Singh, Nitin Vig