Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

Abstract: The present disclosure provides a radiation detector, including a substrate, a pixel array formed on the substrate, a perovskite thick film formed on the pixel array and having a cubic crystal phase, a first electrode formed on the perovskite thick film and is opposite to the pixel array, and a readout circuit. The radiation detector has significantly reduced dark current density and high sensing sensitivity. The present disclosure also provides a method for preparing the perovskite thick film.

Abstract: A multi-power system for providing electrical energy includes a fuel cell unit, a lithium-ion cell unit, and a control unit. The control unit stores a power optimization data sheet that includes multiple power parameter sets, each including a first optimal power and a second optimal power. The control unit is configured to, when operating in a specific mode, select one of the power parameter sets as a selected set, control the fuel cell unit to operate at the first optimal power included in the selected set, control the lithium-ion cell unit to operate at the second optimal power included in the selected set, and control the fuel cell unit and the lithium-ion cell unit to cooperatively output electricity.

Abstract: A method for forming an integrated circuit includes following operations. A substrate is received. The substrate includes a first region, a second region and an isolation structure. The isolation structure has a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed on a portion of the first top surface, a top of the second top surface and the boundary. A dielectric structures is formed over the substrate. Top surfaces of the dielectric structure, the first device, the second device and the dummy structure are aligned with each other. A first metal gate is formed in the first device, and a second metal gate is formed in the second device.

Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to provide haptic feedback in electronic devices based on contextual awareness. According to some aspects, a method of controlling haptic feedback includes obtaining environmental information indicative of an environment of a computing device from at least one sensor and determining a context associated with the mobile device based on the environmental information. The method may include determining haptic feedback for output by the mobile device based on the context.

Abstract: An implant includes a tether and a series of anchors. Each anchor includes (i) a tissue-engaging element, (ii) a head that is slidably coupled to the tether and that includes a lock that is biased to lock in a manner that locks the head to the tether, and (iii) a push-button operatively coupled to the lock. A delivery tool includes a flexible tube that is transluminally advanceable to the heart, and a driver. The driver is configured to, for each of the anchors sequentially, (i) advance the anchor through the flexible tube to the heart while the lock is maintained unlocked by the flexible tube constraining the push-button, (ii) anchor the anchor to tissue of the heart, and (iii) release the push-button by deploying the head out of the flexible tube, the lock responsively locking. Other embodiments are also described.

Abstract: A method for manufacturing an electronic device is provided. The method includes providing a first substrate. The method further includes forming a bank layer on the first substrate. The bank layer includes a bank wall and a first opening, and the first opening adjacent to the bank wall. The method further includes forming a light conversion layer in the first opening. The method further includes forming a spacer on the bank wall. The method further includes providing a second substrate. The method further includes transferring a plurality of electronic units to the second substrate. The method further includes overlapping the first substrate and second substrate, so that the spacer is located between the first substrate and the second substrate.

Abstract: A casing assembly, an electric fan, and a floor scrubber are provided. The casing assembly includes a housing and a cover plate. The housing has an open end. The cover plate has an assembly end connected to the open end. One of the open end and the assembly end is provided with an elastic sealing part, and the other is provided with a fitting part. A first annular projection and a second annular projection are arranged between the elastic sealing part and the fitting part. The first annular projection is located on an inner side of the second annular projection, or vice versa, in the radial direction of the open end. Two ends of the first annular projection abut against the elastic sealing part and the fitting part, respectively. Two ends of the second annular projection abut against the elastic sealing part and the fitting part, respectively.

Abstract: A device includes gate spacers, a gate dielectric layer, and one or more gate metals. The gate spacers are over a substrate. The gate dielectric layer is between the gate spacers. The gate dielectric layer includes a horizontal portion extending parallel to a top surface of the substrate, and vertical portions extending upwards from the horizontal portion. A first one of the vertical portions has a thickness less than a thickness of the horizontal portion.

Abstract: A processor-implemented method for quantization-aware federated training includes quantizing, by a server, a global model. The global model is quantized at multiple different quantization levels for each of one or more subnetwork models to generate one or more quantized subnetwork models. The one or more subnetwork models are assigned to one or more of multiple devices according to device processing capabilities. The server distributes to one or more of the multiple devices, a quantized subnetwork model. The server receives a model update from the one or more devices based on local data. The server generates an updated global model according to an aggregation function based on the model update from each of the one or more devices.

Abstract: Devices, assemblies and methods for fixing a telecommunications cable. In certain embodiments, a cable fixation unit that can clamp a cable jacket also includes legs having feet that are mountable to a slotted support structure by inserting the feet into the support structure's slots in a sequence of motions.

Abstract: An object tracking system and an object tracking method are provided. The object tracking system includes a transmitter, a receiver and at least one processing circuit. The transmitter is configured to transmit wireless signals through a target space. The receiver is configured to receive the wireless signals. The at least one processing circuit is configured to perform following processes: obtaining the wireless signals received by the receiver; generating motion information associated with at least one target object by executing a motion machine-learning model that processes the received wireless signals; and generating three-dimensional tracking information of the at least one target object with respect to the target space by fusing spatial information of the target space and the motion information.

Abstract: A plastic dehumidification and drying device includes a dehumidification host system, an air supply system and at least one plastic processing system. The air in the dehumidification host system is cooled by the host windmill through a secondary condenser and enters a host honeycomb runner. The host honeycomb runner uses a host regeneration windmill and a host regeneration heater to send regeneration air to help absorb moisture. The host honeycomb runner sends the dehumidified air to the plastic processing system for drying plastics. The air returns to the dehumidification host system and passes through the host filter, then the closed cycle is carried out through the primary condenser and the host windmill. The primary condenser and the secondary condenser are provided with ice water to cool the moisture in the contracted air. The air supply system supplies air to the dehumidification host system to supplement the pressure loss, further reduce the dew point and increase the efficiency of dehumidification.

Abstract: Operations to recognize clock ports within a simulation circuit component and/or recognize a clock signal within simulation waveforms are described. One or more of the operations include generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component. The operations also include calculating a correlation vector based on bit sequences in the input values and bit sequences in the output values. The first input port is determined to be a clock port by applying a machine learning model to the correlation vector.

Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.

Abstract: A semiconductor structure includes a first well, a second well, a first doping region, a second doping region, a field oxide layer, a third well, and a fourth well. The first well is N-type. The second well is P-type, adjacent to the first well and in contact with the first well at an interface. The first doping region is N-type and deposited in the first well. The second doping region is P-type and deposited in the second well. The field oxide layer is formed in the first well and deposited between the first doping region and the second doping region. The third well is N-type, formed in the first well, and deposited below the field oxide layer. The fourth well is N-type, formed in the first well, and deposited below the field oxide layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

Abstract: A drink pouch includes an outer bag and an inner bag. The inner bag is floatingly disposed in the outer bag. The inner bag contains at least one brewable substance. A porous structure is formed on a surface of the inner bag. Water is able to be filled in the outer bag and brew the at least one brewable substance in the inner bag through the porous structure to form a beverage.

Abstract: A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.