Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a dielectric layer, a source electrode, a drain electrode, and a diode structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The dielectric layer is disposed on the gate electrode. The source electrode and the drain electrode are disposed on opposite sides of the gate electrode and in contact with the channel layer, respectively. The diode structure is disposed on the dielectric layer and is electrically connected to the source electrode.

Abstract: A transistor includes a channel layer, a gate stack, and source/drain regions. The channel layer includes a graphene layer and hexagonal boron nitride (hBN) flakes dispersed in the graphene layer. Orientations of the hBN flakes are substantially aligned. The gate stack is over the channel layer. The source/drain regions are aside the gate stack.

Abstract: An interactive control device includes a housing, a touch display panel and a face cover. The touch display panel is disposed within the housing. The face cover has a front surface and a rear surface. A first hollow configuration is formed on the front surface of the face cover, the face cover is detachably assembly with the housing and placed over the touch display panel, and a display area and a touch area of the touch display panel are limited by the first hollow configuration.

Abstract: A computing system includes: a first input device for receiving a first input data from a user, the first input device includes a computing module for processing a data inputted from the first input device and generating an output data; and a head mounted display, telecommunicatively connected to the first input device by a communication module, for receiving the output data and displaying a binocular virtual image related to the output data; wherein the head mounted display has a first light direction adjuster and a second light direction adjuster for changing the direction of a first light signal and a second light signal emitted by a first emitter and a second emitter respectively, such that the first light signal and the second light signal are emitted relative to the first angle and the second angle of the user's frontal plane towards a first eye and a second eye respectively.

Abstract: The present disclosure relates to mir-17˜92 as a candidate therapeutic or diagnostic target of motor neuron (MN) degeneration diseases. Expression of mir-17˜92 is sustained throughout adulthood in spinal MNs and specifically decreases before the onset of MN loss in SOD1G93A mice. Accordingly, mir-17˜92 can be used as a candidate therapeutic target for ALS.

Abstract: Various aspects generally relate to routing web traffic over multiple internet protocol (IP) interfaces. For example, a user equipment (UE) may receive a request to open, in parallel, multiple transmission control protocol (TCP) socket connections associated with hypertext transfer protocol (HTTP) traffic, distribute the multiple TCP socket connections among multiple available IP interfaces, and route the HTTP traffic associated with the multiple TCP socket connections over the multiple IP interfaces. Additionally, or alternatively, the UE may receive a request to open a user datagram protocol (UDP) socket associated with QUIC traffic, select, from multiple available IP interfaces, a current IP interface that has a best quality of service (QOS) metric, and route the QUIC traffic associated with the UDP socket over the current IP interface. Numerous other aspects are described.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A degradable composite, a wind turbine blade, and a manufacturing method of the wind turbine blade are provided. The degradable composite includes 30% to 40% of a degradable epoxy resin composition, 45% to 55% of a fiber raw material, 0% to 20% of a core material, and 0% to 10% of an epoxy structural adhesive in mass percentages. The degradable epoxy resin composition includes a degradable modified resin. A degradable epoxy resin is adopted as a structural layer to manufacture a wind turbine blade that has excellent mechanical properties and conforms to the requirements of blade designs and the environment, health, and safety (EHS) standards in the industry. Because the degradable epoxy resin is used, the manufactured composite component can be degraded and separated under appropriate conditions to recover a resin liquid and a fiber raw material, and the recovered resin liquid and fiber raw material can be recycled.

Abstract: Vehicle window glass is provided. The vehicle window glass includes outer glass, inner glass, and an interlayer connected between the outer glass and the inner glass. The outer glass has a first tempered region and a second tempered region. The first tempered region is connected to the second tempered region. A surface stress of the first tempered region is greater than a surface stress of the second tempered region. A vehicle is further provided.

Abstract: A smart projection vehicle lamp includes laser light sources, two-dimensional MEMS mirrors, focusing lenses, a reflective phosphor plate, a narrow-band blue light reflector, and a lens group. The two-dimensional MEMS mirrors are correspondingly arranged on paths of laser light beams of the laser light sources. The laser light beams are dynamically reflected by the two-dimensional MEMS mirrors. The reflective phosphor plate has a phosphor layer and a reflective layer located on one side of the phosphor layer. The narrow-band blue light reflector is disposed between the focusing lenses and the reflective phosphor plate, and has a reflective band and a transmissive band. The converged laser light beams are reflected by the reflective band and illuminate the reflective phosphor plate. The laser light beams excite the phosphor layer and are mixed into visible light reflected by the reflective layer and passes through the transmissive band to be emitted outward.

Abstract: A BIOS backup/recovery system includes a chassis housing a BIOS backup/recovery subsystem coupled to a primary and a secondary BIOS storage system. The BIOS backup/recovery subsystem begins initialization operations and determines whether the primary BIOS storage system includes customized MAC addresses. If so, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match the customized MAC addresses in the primary BIOS storage system and, if not, performs a BIOS backup operation that includes copying the customized MAC addresses in the primary BIOS storage system to the secondary BIOS storage system. If not, the BIOS backup/recovery subsystem determines whether MAC addresses in the secondary BIOS storage system match default MAC addresses in the primary BIOS storage system and, if not, performs a BIOS recovery operation that includes copying customized MAC addresses in the secondary BIOS storage system to the primary BIOS storage system.

Abstract: A hardware-based fan controller for controlling fan modules in a computer system having multiple computer nodes is disclosed. Each of the computer nodes has a service processor. The fan controller includes a slave module that receives fan speed commands from each of the service processors. A fan speed generator is coupled to the slave module and a subset of the fan modules. The fan speed generator receives fan speed commands from the slave module and fan speed outputs from the subset of fan modules. The fan speed generator is configured to output a speed command to each of the fan modules in the subset.

Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.

Abstract: A method for manufacturing a semiconductor device includes forming a first CPODE dummy poly gate and a second CPODE dummy poly gate on a semiconductor substrate; removing the first CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a first trench extending into the semiconductor substrate; filling the first trench with a first dielectric material to form a first isolation structure to isolate the first and second transistors from each other; removing the second CPODE dummy poly gate and a portion of the semiconductor substrate therebelow to form a second trench extending into the semiconductor substrate; and filling the second trench with a second dielectric material having a dielectric composition different from that of the first dielectric material to form a second isolation structure to isolated the third and fourth transistors from each other.

Abstract: Systems and techniques are described herein for modifying the scale and/or position of objects in images. For instance, a system can obtain a two-dimensional (2D) input image from a camera and a three-dimensional (3D) representation of the 2D input image. The system can further determine a first portion of the 3D representation of the 2D input image corresponding to a target object in the 2D input image. The system can adjust a pose of the first portion of the 3D representation of the 2D input image corresponding to the target object. The system can further generate a 2D output image having a modified version of the target object based on the adjusted pose of the first portion of the 3D representation of the 2D input image corresponding to the target object to be output on a display.

Abstract: A linear power converter circuit comprising: an output transistor, wherein a gate of the output transistor is controlled by an error amplification signal for converting an input voltage into an output voltage; an error amplification circuit configured to amplify a difference between a reference voltage and a feedback voltage to generate the error amplification signal, thereby regulating the output voltage to a predetermined level, wherein the feedback voltage is related to the output voltage; and a first surge protection circuit configured to clamp the gate-source voltage of the output transistor when the slew rate of the input voltage exceeds a threshold, thereby limiting the current through the output transistor to not exceed a predetermined upper limit.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. The first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.

Abstract: An operation method of a software program meeting UEFI specifications for configuring a GPIO port is provided. The operation method includes: operating in a command-line mode to display, on a display device, a first prompt for guiding a user to input a string of command-line arguments; in response to receipt of a string of command-line arguments for reading content stored in a register that corresponds to one of GPIO pins of the GPIO port under the command-line mode, displaying, on the display device, a default value of the register that corresponds to a function of said one of the GPIO pins; and in response to receipt of a string of command-line arguments for setting a register that corresponds to one of the GPIO pins to a set value under the command-line mode, writing the set value to the register to replace a current value with the set value.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.