Abstract: A parallel-type coating apparatus for coating at least one object to be coated carried by a carrier includes a double-layer vacuum chamber having feed and discharge chambers opposite to each other in a Z-direction, and a plurality of process chambers for performing at least a fixed point coating on the at least one object to be coated. The double-layer vacuum chamber and the process chambers are arranged in two juxtaposed rows in a Y-direction transverse to the Z-direction. A feed lifting mechanism is disposed in one of the double-layer vacuum chamber 3 and the process chambers, and includes a feed lifting seat movable in the Z-direction. A plurality of first conveying devices are respectively disposed in the other ones of the process chambers for conveying the carrier. A method for coating a multilayer film on at least one object to be coated carried by a carrier is also disclosed.

Abstract: An automatic control system for a phase angle of a motor is provided. A current detector circuit detects a current signal of the motor to output a current detected signal. A control circuit outputs a control signal according to the current detected signal indicating a time point at which the current signal reaches a zero value. A driver circuit outputs a driving signal according to the control signal. An output circuit operates to output a motor rotation adjusting signal to the motor to adjust a rotational state of the motor according to the driving signal.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a substrate, and forming a first isolating layer, a first stabilizing layer, a second isolating layer and a second stabilizing layer, which are sequentially stacked onto one another, on the substrate; forming a through hole penetrating through the first isolating layer, the first stabilizing layer, the second isolating layer and the second stabilizing layer, and forming a lower electrode on a side wall and a bottom portion of the through hole; removing a portion of a thickness of the second stabilizing layer to expose a portion of the lower electrode; forming a mask layer on a side wall of the exposed lower electrode; and etching the second stabilizing layer by using the mask layer as a mask to form a first opening.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: The present invention relates to the field of detection of dimethyltryptamine. In order to solve the problems in the prior art that liquid chromatography-tandem mass spectrometry for detection of dimethyltryptamine has high requirements for instruments and operators and is difficult to popularize and low in detection speed, the present invention discloses a dimethyltryptamine hapten, an artificial antigen and preparation methods and application thereof. The dimethyltryptamine hapten is obtained by a reaction of N,N-dimethyl-5-hydroxytryptamine as a precursor and glutaric anhydride. The artificial dimethyltryptamine antigen obtained from the dimethyltryptamine hapten can be used for preparing a dimethyltryptamine monoclonal antibody and a dimethyltryptamine colloidal gold-fluorescence test paper.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A device includes a substrate having a first surface and a second surface opposite to the first surface; a thin-film transistor array disposed on the first surface, including a plurality of transistors; a plurality of diodes disposed on the thin-film transistor array; a plurality of conductive structures penetrating through the substrate from the first surface to the second surface, wherein the plurality of conductive structures are corresponding to the plurality of diodes and electrically connected to the plurality of diodes; a driver unit disposed on the second surface of the substrate; a patterned conductive layer disposed between the substrate and the driver unit; a protection layer disposed on the patterned conductive layer, wherein the protection layer has an opening that exposes the patterned conductive layer; and a conductive material disposed in the opening.

Abstract: A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

Abstract: An ablation catheter and an ablation system are provided. The ablation catheter includes a sheath and an ablation assembly. The ablation assembly is disposed at a distal end of the sheath for performing ablation and isolation on a target tissue area. The ablation system includes the ablation device and a mapping device, the mapping device includes a mapping electrode arranged at a distal end of the ablation catheter, and the mapping electrode is used for collecting electrophysiological signals in the target tissue area.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.

Abstract: A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.

Abstract: An electronic substrate and an electronic device are provided. The electronic substrate includes a base, a protruding portion, and a bonding pad. The protruding portion and the bonding pad are disposed on the base. The bonding pad is not overlapped with a boundary of the protruding portion.

Abstract: A manufacturing method of a thermoplastic composite bicycle frame comprises a shell forming step: turning thermoplastic composite laminates into shells being assemblable by compression molding, wherein each shell has a cavity surrounded by the shell, at least one straight segment and at least one curved segment connected with each other, the straight segments are aligned with one another, the curved segments are aligned with one another, each straight segment has a straight connecting edge, and each curved segment has a curved connecting edge; a shell assembling step: assembling the shells to make the straight connecting edges overlapped with one another and to make the curved connecting edges butt jointed with one another; and a hot pressing step: turning the straight connecting edges and the curved connecting edges into fusion areas by heating and compressing so as to connect the shells as a bicycle frame component.

Abstract: The present disclosure relates to an image sensor integrated chip (IC). The image sensor IC includes one or more interconnects arranged within an inter-level dielectric (ILD) structure on a first side of a substrate. An image sensing element is arranged within the substrate. Sidewalls of the substrate form one or more trenches extending from a second side of the substrate to within the substrate on opposing sides of the image sensing element. A dielectric structure is arranged on the sidewalls of the substrate that form the one or more trenches. A conductive core is arranged within the one or more trenches and is laterally separated from the substrate by the dielectric structure. The conductive core is electrically coupled to the one or more interconnects.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: The presently disclosed subject matter provides for methods and compositions for treating multiple myeloma. It relates to chimeric antigen receptors (CARs) that specifically target a G-protein coupled receptor (e.g., a G-protein coupled receptor family C group 5 member D (GPRC5D)), and immunoresponsive cells comprising such CARs. The presently disclosed CARs targeting a G-protein coupled receptor (e.g., GPRC5D) have enhanced immune-activating properties, including anti-tumor activity.