Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: An exemplary two-step method for power system inertia online estimation is described. The first step is to accurately estimate the POI-level aggregated inertia. The second step is to calculate the system-level inertia constant by weighting all the POI-level aggregated inertia and to monitor the inertia spatial distribution. In one example embodiment, the PMU is installed at POI, the frequency spatial difference is considered, and the mechanical power is carefully treated.

Abstract: A powder-based three-dimensional printing (3DP) method, device and system, and a computer-readable storage medium. The method includes: analyzing printing images of layers corresponding to a part to be printed to determine a target print image and adding a preset mark to the target print image which includes a print image of a target layer that causes a previous powder layer of the target layer to displace during printing; acquiring an image to be printed of a current layer to be printed; identifying the image to be printed to determine whether the preset mark exists on the image to be printed; and if yes, processing the current layer to be printed and/or a previous powder layer of the current layer to be printed such that the previous powder layer of the current layer does not move with powder spreading of the current layer.

Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.

Abstract: An electronic device includes a back board, a circuit board, a first attaching member and a second attaching member. The circuit board is arranged on the back board. The first attaching member is arranged between the back board and the circuit board. The second attaching member is arranged between the back board and the circuit board. The circuit board is fixed on the back board through the first attaching member and the second attaching member, and a material of the first attaching member is different from that of the second attaching member.

Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.

Abstract: A substrate processing apparatus, comprising: a processing chamber having a plasma intake wall configured to receive plasma from a remote plasma source (RPS) and a surrounding wall having an inner surface defining an interior volume for receiving a substrate; and a substrate support having a substrate supporting surface facing the plasma intake wall and elevatably arranged in the interior volume of the processing chamber. The surrounding wall, in a cross-section of the processing chamber, includes: a first segment having a first width associated with a processing region for the substrate support; a second segment having a width greater than the first width that is further away from the plasma intake wall than the first segment.

Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.

Abstract: Disclosed are an interactive information processing method, an electronic device and a storage medium. The method includes establishing a position correspondence between a display text generated based on a multimedia data stream and the multimedia data stream; and presenting the display text and the multimedia data stream corresponding to the display text based on the position correspondence.

Abstract: The present disclosure relates to a radiation system. The system may include a treatment assembly, an imaging assembly, a first gantry, and a second gantry. The treatment assembly may include a first radiation source configured to deliver a treatment beam and have a treatment region. The first gantry may be configured to support the first radiation source. The imaging assembly may include a second radiation source and a radiation detector. The second radiation source may be configured to deliver an imaging beam and the radiation detector may be configured to detect at least a portion of the imaging beam. The imaging assembly may have an imaging region. The second gantry may be configured to support the second radiation source and the radiation detector, wherein the second radiation source is located within the second gantry. The treatment region and the imaging region at least partially overlap.

Abstract: A component for a vehicle interior may comprise a light guide to allow light transmission from a light source for a user interface, and a cover to cover the light guide. The user interface may be presented at the cover. The cover may comprise a depression in an inner surface of the cover and the light guide may comprise a projection comprising a light-transmissive resin fit within the depression. The projection may comprise an icon to be presented at the user interface when illuminated, and to be hidden by the cover when not illuminated. The user interface may comprise a light display and an input device connected to a sensor. The icon may comprise an image. The cover thickness may be greater than the projection height. The component may comprise a steering wheel, console, floor console, center console, instrument panel, door panel, dashboard, display, armrest, or cockpit.

Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a first device, a second device, and a processor communicatively coupled to the expansion interface. The expansion interface includes a plurality of slots. Two slots of the plurality of slots are controlled by a single reset signal. The first device is connected to a first slot of the two slots and has a feature that is compatible with the single reset signal. The second device is connected to a second slot of the two slots and does not have the feature compatible with the single reset signal. The process is to detect the first device connected to the first slot and the second device connected to the second slot and disable the feature by preventing the first slot and the second slot from receiving the single reset signal.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: A semiconductor device includes a substrate, a first multilayer capacitor, and a second multilayer capacitor. The first multilayer capacitor includes a first plurality of conductive layers. The semiconductor device further includes a first set of contacts including a first contact electrically connected to a first conductive layer, and a second contact electrically connected to a second conductive layer, wherein the first contact is spaced from the second contact by a first distance. The second multilayer capacitor includes a second plurality of conductive layers. The semiconductor device further includes a second set of contacts including a third contact electrically connected to a third conductive layer, and a fourth contact electrically connected to a fourth conductive layer, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.