Patents by Inventor An-Chi CHENG

An-Chi CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8570361
    Abstract: An exemplary decoding method of an input video bitstream including a first bitstream and a second bitstream includes: decoding a first picture in the first bitstream; after a required decoded data derived from decoding the first picture is ready for a first decoding operation of a second picture in the first bitstream, performing the first decoding operation; and after a required decoded data derived from decoding the first picture is ready for a second decoding operation of a picture in the second bitstream, performing the second decoding operation, wherein The first bitstream contains pictures of a first view for a 3D video presentation, the second bitstream contains pictures of a second view for the 3D video presentation, and a time period of decoding the second picture in the first bitstream and a time period of decoding the picture in the second bitstream are overlapped in time.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: October 29, 2013
    Assignee: Mediatek Inc.
    Inventors: Te-Chi Hsiao, Yung-Chang Chang, Ching-Chieh Wang, Shih-Hung Lin, Chi-Cheng Ju
  • Publication number: 20130271396
    Abstract: A display includes a display module and a sensing module including a proximity sensing electrode, a set of sensing electrodes, a touch circuit, a proximity circuit and a processor. The sensing electrodes are configured to sense a touch input during a first period and sense a proximity input during a second period. The touch circuit is coupled to the sensing electrodes for controlling the sensing electrodes to sense the touch input in the first period, and converting a two-dimensional analog touch signal transmitted from the set of the sensing electrodes to a two-dimensional digital touch signal. The proximity circuit is coupled to the sensing electrodes and the proximity sensing electrode for controlling the sensing electrodes and the proximity sensing electrode to sense the proximity input, and converting a three-dimensional analog proximity signal transmitted from the set of sensing electrodes and proximity unit to a three-dimensional digital proximity signal.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 17, 2013
    Applicant: AU OPTRONICS CORP.
    Inventors: Chi-Cheng Chen, Chao-Chen Wang, Kyaw Kyaw Tun, Chih-Hao Hu
  • Publication number: 20130264668
    Abstract: A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Chi-Cheng Hung, Jun-Nan Nian, Chih-Chung Chang
  • Publication number: 20130258652
    Abstract: A light-guiding element, an illumination module and a laminate lamp apparatus are provided. The light-guiding element comprises an upper reflection member extended along a longitudinal axis direction, and a lower reflection member extended along the longitudinal axis direction thereof and coupled to the upper reflection member. The lower reflection member comprises a first reflective portion with at least a first inclined flat plate, and the upper reflection member comprises a second reflective portion facing towards the first reflective portion. A light placement portion and a light outputting trough are formed between the first reflective portion and the second reflective portion. The light outputting trough is gradually expanded largely according to a direction of being away from the light placement portion.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 3, 2013
    Applicant: Lextar Electronics Corporation
    Inventors: Shang-Jung HSIEH, Chun-Hung LIU, Chi-Cheng CHENG, Sheng-Ping CHEN
  • Patent number: 8546226
    Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ming Wang, Ping-Chia Shih, Chun-Sung Huang, Chi-Cheng Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
  • Patent number: 8546871
    Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Cheng Huang, Ping-Chia Shih, Chih-Ming Wang, Chun-Sung Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
  • Publication number: 20130243100
    Abstract: Method and system of video decoding incorporating frame compression to reduce frame buffer size are disclosed. The method adjusts parameters of the frame compression according to decoder system information or syntax element in the video bitstream. The decoder system information may be selected from a group consisting of system status, system parameter and a combination of system status and system parameter. The decoder system information may include system bandwidth, frame buffer size, frame buffer status, system power consumption, and system processing load. The syntax element comprises reference frame indicator, initial picture QP (quantization parameter), picture type, and picture size. The adaptive frame compression may be applied to adjust compression ratio. Furthermore, the adaptive frame compression may be applied to a decoder for a scalable video coding system or a multi-layer video coding system.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: MEDIATEK INC.
    Inventors: Tsu-Ming Liu, Yung-Chang Chang, Chi-Cheng Ju
  • Patent number: 8536283
    Abstract: A varnish composition includes (1) a benzoxazine resin having highly symmetric molecular structure; (2) at least one of naphthol novolac resins, aniline novolac resins and phenolic novolac resins; (3) fillers. The benzoxazine resin having highly symmetric molecular structure, and the at least one of naphthol novolac resins, aniline novolac resins and phenolic novolac resins contribute to increase the glass transition temperature of the varnish composition, while decrease the coefficient of thermal expansion and moisture absorbability due to their small and highly symmetric molecular structures. A copper substrate can meet the requirement of high glass transition temperature (TMA?200° C.) and low coefficient of thermal expansion (?1/??30/135 (?m/m° C.). Therefore, the composition of the invention can be widely used as high-performance electronic material.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 17, 2013
    Assignee: Nan Ya Plastics Corporation
    Inventors: Ming-Jen Tzou, Chi-Cheng Chen, Mei-Ling Chen
  • Publication number: 20130234252
    Abstract: An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hsiang-Chen LEE, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
  • Patent number: 8526149
    Abstract: A limiting current circuit that has output short circuit protection is connected to an external voltage source and comprises an output terminal, an input current unit, a driving transistor, a voltage control resistor, a voltage control transistor and a delay unit. The output terminal is connected to a load and has an output current. The driving transistor has an internal resistance, a drain current and a gate voltage. The voltage control resistor has a resistor voltage. The voltage control transistor has an internal resistance and a parasitic capacitance. The delay unit makes the resistor voltage charging the parasitic capacitance to extend the period of lower internal resistance of the voltage control transistor and the period of higher internal resistance of the driving transistor, makes the internal resistance of the voltage control transistor is less than the internal resistance of the driving transistor when the load is shorted.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: September 3, 2013
    Assignee: Advanced-Connectek Inc.
    Inventors: Ching-Chi Cheng, Wen-Hsiang Chien
  • Publication number: 20130221424
    Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 29, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee
  • Patent number: 8513670
    Abstract: A pixel structure and a pixel circuit having multi-display mediums are provided. A storage capacitor and a first display medium are disposed in different layers, so as to overlap the storage capacitor with a pixel electrode of the first display medium. Accordingly, an area of the first display medium can be increased for enlarging an aperture ratio of the pixel. Furthermore, because a third pixel electrode is disposed in a conductive layer, the third pixel electrode can control/drive a second display medium under a substrate.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: August 20, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Yen-Shih Huang, Chen-Wei Lin, Hua-Chi Cheng
  • Patent number: 8513790
    Abstract: A package-base structure of a luminescent diode and its fabricating process. The package-base structure includes a substrate having thereon a holding space; an insulating layer extending from a bottom surface of the holding space to the bottom of the substrate; an through hole defined in the insulating layer; and a conductive layer disposed over the insulating layer. The insulating layer decouples the current flow and heat flow to increase the lifetime of the package-base structure together with the luminescent diode. In the fabricating process, the insulating layer is formed by anodic etching to allow the insulating layer have a porous structure.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: August 20, 2013
    Assignee: Silicon Base Development Inc.
    Inventors: Chih-Ming Chen, Deng-Huei Hwang, Ching-Chi Cheng
  • Publication number: 20130206844
    Abstract: A protective cover of a mobile electronic product capable of adding a backup battery to the exterior of the mobile electronic product, and the mobile electronic product is connected to the backup battery. In the protective cover of the mobile electronic product, a RFID module is installed for applying the mobile electronic product in a non-contact access identification device or a secured transaction device. The backup battery can supply electric power to the mobile electronic product to overcome the difficulty of accessing backup power.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Inventors: SHIH-HUI CHEN, Chin-Tien Lin, Hua-Chi Cheng
  • Publication number: 20130208468
    Abstract: A lighting device is provided. The lighting device includes an optical reflection plate, a light holder, and at least one light source. The optical reflection plate includes a non-reflective region located in the center of the optical reflection plate, and a plurality of reflection regions surrounding the non-reflective region in sequence. The light holder is located on the non-reflective region of the optical reflection plate and includes a circle side-light concave portion. A light-emitting opening of the side-light concave portion faces to the reflection regions. The light source is located in the side-light concave portion of the light holder. When the light source emits light, the light emitted from the light source is reflected by the reflection regions.
    Type: Application
    Filed: July 13, 2012
    Publication date: August 15, 2013
    Applicant: LEXTAR ELECTRONICS CORPORATION
    Inventors: Sheng-Ping Chen, Chi-Cheng Cheng, Chun-Hung Liu, Shang-Jung Hsieh
  • Patent number: 8487733
    Abstract: A composite magnetic core assembly includes an inner magnetic core and an outer magnetic core. The inner magnetic core is made of a high saturation flux density and low permeability material. The outer magnetic core is made of a low saturation flux density and high permeability material. The outer magnetic core includes a ring-shaped wall and a receptacle. The inner magnetic core is accommodated within the receptacle.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: July 16, 2013
    Assignee: Delta Electronics, Inc.
    Inventors: Jiang Chu, Wei Chen, I-Chi Cheng, Yi-Fan Wu, Zhi Huang
  • Publication number: 20130170174
    Abstract: A Multi-Cavities light emitting device includes a base, a blue light emitting unit, at least two red light emitting units, a light conversion layer and a lens, and the base has a central slot and at least two side slots symmetrically formed on external sides of the central slot, and the blue light emitting unit is installed in the central slot, and the two red light emitting units are installed in the two side slots respectively, and the light conversion layer is covered onto the blue light emitting unit, and the lens is protruded from the base and sealed onto the central slot and at least two side slots, so as to achieve the effects of improving the light extraction efficiency of an LED chip and the yield rate of the product and reducing the overall assembling time and cost.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventors: Hsi-Yan CHOU, Tzu-Chi Cheng
  • Publication number: 20130167757
    Abstract: An adjustable desk includes a desk board, a supporting unit, and a first adjusting unit. The desk board includes front and rear ends. The supporting unit disposed between the desk board and the ground includes a first leg pivotally connected with the front end. The first adjusting unit mounted between the desk board and the first leg includes a screw shaft, at least one linkage, and at least one level. The linkage is engaged screwedly with screw shaft. The level pivotally connected between the linkage and the rear end. While the screw shaft is rotated, the linkage is moved axially between two ends of the outer screw portions to drive the level pivoting with respect to the screw shaft. The desk board is pivoted with respect to the first leg to adjust a slope angle formed between the desk board and the supporting unit steplessly without tools.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Inventors: Chi-Cheng Tsai, Te-Ju Hsieh
  • Patent number: 8477841
    Abstract: A video processing method is implemented by encoding and decoding devices. The video processing method includes: configuring the encoding device to decrease a resolution of a received at least one source image frame based on a received reference signal to obtain reduced image frame content with a reduced resolution, and to generate a relay image frame containing the reduced image frame content; configuring the encoding device to generate a header including at least one element containing information of the reduced image frame content, pack the relay image frame and the header into a video signal, and transmit the video signal to the decoding device; and configuring the decoding device to obtain a restored image frame from the reduced image frame content based on the element in the header. A data structure, and encoding and decoding devices are also disclosed.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: July 2, 2013
    Assignee: Acer Incorporated
    Inventors: Hsin-Yuan Peng, Chi-Cheng Chiang
  • Publication number: 20130163217
    Abstract: An electronic system includes a first circuit board having a first connection interface, and a second circuit board having a second connection interface and a guide pin device. The guide pin device includes a convex connector and a concave connector. The convex connector includes a guide member and a connection portion. The connection portion connects the guide member to the first circuit board and has two first inclined surfaces formed on two opposite sides of the guide member. The concave connector is secured on the second circuit board and includes a guide sliding slot and two second inclined surfaces formed on two opposite sides of the guide sliding slot. When the guide member is aligned with and is inserted into the guide sliding slot, the two first inclined surfaces mat with the two second inclined surfaces, and the first connection interface is engaged with the second connection interface.
    Type: Application
    Filed: April 9, 2012
    Publication date: June 27, 2013
    Applicant: INVENTEC CORPORATION
    Inventors: Chun-Ying YANG, Chi-Cheng HSIAO