Patents by Inventor An-Chun Chen

An-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190321251
    Abstract: A lift assist device includes a base, a lifting mechanism and a fixing unit. The base stands on the ground. The lifting mechanism is disposed at the base and moves reciprocally along a lifting direction. The fixing unit is connected with and actuated by the lifting mechanism, and the fixing unit is configured to be fixed to the body of a user. The extension line of the lifting direction is not perpendicular to the ground.
    Type: Application
    Filed: August 28, 2018
    Publication date: October 24, 2019
    Inventors: YUN-PIN CHEN, YUN-WEI HSIEH, KUAN-CHUN CHEN
  • Publication number: 20190327266
    Abstract: A computer network endpoint is secured to prevent information leak or other compromise by instantiating in memory first, second and third security zones. With respect to an authorized user, the first zone is readable and writable, the second zone is read-only, and the third zone is neither readable nor writable. System information (e.g., applications, libraries, policies, etc.) are deployed into the first zone from the second zone. When sensitive data is generated in the first zone, e.g., when a secure communication session is established using a cryptographic key, the sensitive data is transferred from the first zone to the third zone, wherein it is immune from information leak or other compromise. The sensitive information is transferable from the third zone to one or more external having a need to know that information. Because information does not pass directly from the first security zone to the external systems, the endpoint is secured against information leak or other attack.
    Type: Application
    Filed: June 29, 2019
    Publication date: October 24, 2019
    Applicant: International Business Machines Corporation
    Inventors: Kuo-Chun Chen, Wei-Hsiang Hsiung, Sheng-Tung Hsu, Fadly Yahaya
  • Publication number: 20190327222
    Abstract: An embodiment of the invention may include a method, computer program product and system for secure authentication within a communication protocol session. The embodiment may include retrieving, by a client computer of the TLS session, a challenge string associated with the TLS session. The embodiment may include generating, by the client computer, a first digest based on the challenge string and authentication information of a user of the client computer. The embodiment may include sending, by the client computer, the first digest to a server of the TLS session. The retrieving, generating and sending, by the client computer, are carried out after the TLS session has been established between the client computer and the server.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Sheng-Tung Hsu, Wei-Hsiang Hsiung, Kuo-Chun Chen, Wayne Chou
  • Patent number: 10453939
    Abstract: Embodiments of the invention are directed to a vertical FET device having gate and source or drain features. The device includes a fin formed in a substrate and a source or a drain region formed in the substrate. The device further includes a trench formed in the source or the drain region and a dielectric region formed in the trench. The device further includes a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region includes at least a portion of the dielectric region. In some embodiments, the device further includes a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further includes at least a portion of the bottom spacer.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10454946
    Abstract: Selecting a receive side scaling (RSS) key is provided. It is determined whether a defined time interval expired. In response to determining that the defined time interval has expired, it is determined whether one or more keys in a set of randomly generated candidate RSS keys have a higher packet distribution score than an active RSS key. In response to determining that one or more keys in the set of randomly generated candidate RSS keys have a higher packet distribution score than the active RSS key, an RSS key having a highest packet distribution score is selected from the one or more keys in the set of randomly generated candidate RSS keys that have a higher packet distribution score than the active RSS key. The RSS key having the highest packet distribution score is used to distribute incoming network packets across a plurality of processors.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Wen Chao, Kuo-Chun Chen, Wei-Hsiang Hsiung, Sheng-Tung Hsu, Ming-Pin Hsueh
  • Patent number: 10450545
    Abstract: This invention relates to microfluidic chips for and their applications in acquiring sperms with high velocity and/or motility. The microfluidic chip comprises an inlet region, a first flow channel, a divergent channel, an optional block structure with rounded corners and one or more outlet region(s). The invention mimics sperm activation process in body and designs a microfluidic chip mimicking the activation process so that higher amount of populations and/or subpopulations of sperms with high motility can be acquired.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 22, 2019
    Assignees: NATIONAL TSING HUA UNIVERSITY, TAIPEI MEDICAL UNIVERSITY
    Inventors: Richard Li-Chern Pan, Fan-Gang Tseng, Jen-Kuei Wu, Peng-Chun Chen
  • Publication number: 20190317129
    Abstract: An insulator applied in a probe base including a probe mounting hole, the insulator is a sheet structure having plural through holes, and the probe mounting hole is formed at the center of the insulator, and the probe mounting hole and the through hole penetrate from a first surface to a second surface of the insulator, and the regions of the first and second surfaces without the probe mounting hole and the through hole are coplanar. The probe base has a base body and at least a composite assembly, and the base body has at least a testing zone, and the composite assembly is installed in the testing zone and has at least a probe hole for installing a probe, and the insulator is installed into the probe hole.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Inventors: CHIEN-YU HSIEH, YEN-CHUN CHEN, CHIH-HUI HOU, WEI-CHU CHEN, YEN-HUI LU, TING-CHEN PAN, YEN-WEI LIN, BOR-CHEN TSAI
  • Publication number: 20190319401
    Abstract: A high-speed connector for an automobile includes a wire terminal connector, a board terminal connector connected to the wire terminal connector, and elastic sliding blocks provided on two sides of the wire terminal connector. The sliding blocks on two sides are configured separately or are integrated together. The wire terminal connector includes a housing, a contact body and a wire rod. The contact body is installed in the housing. The contact body contacts and is connected to the board terminal connector. The wire rod is connected to the contact body and protrudes out of the housing. The housing includes a main body portion and side snap-fit plates provided on two sides of the main body portion. A side snap-fit groove is provided on the side snap-fit plate. Side snap-fit clasps are provided on two sides of the board terminal connector.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 17, 2019
    Applicant: Amphenol AssembleTech(Xiamen) Co.,Ltd
    Inventors: Wenchu YANG, Chun CHEN, Haitao XIONG, Dejie KONG, Siting LIAO, Jianming CHEN, Hang LI, Xiyin ZHOU
  • Patent number: 10446245
    Abstract: A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Yoram Betser, Kuo Tung Chang, Amichai Givant, Shivananda Shetty, Shenqing Fang
  • Patent number: 10447008
    Abstract: A laser driver device is provided, which includes a control circuit, a driver circuit and a feedback circuit. The control circuit receives setup data and convert the setup data into a setup signal. The driver circuit receives the setup signal and generates a drive current according to the setup signal to drive a laser light source. The feedback circuit receives the setup data and the feedback signal of the laser light source and compares the setup data with the feedback signal to generate an adjust signal. The driver circuit receives the adjust signal and adjusts the drive current according to the adjust signal.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: October 15, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Cheng Song, Chih-Chun Chen, Fu-Shun Ho, Chien-Hung Lu
  • Patent number: 10439031
    Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20190299942
    Abstract: The present disclosure relates to methods and associated systems for operating a battery exchange station. The present technology (1) receives battery information from a memory attached to each of a plurality of exchangeable batteries positioned in the battery exchange station; (2) receives a battery demand prediction associated with the battery exchange station; and (3) identifying one or more uninterruptible-power-supply (UPS) batteries from the plurality of exchangeable batteries at least partially based in part on the battery demand prediction and individual state of charges (SoCs) of the plurality of exchangeable batteries.
    Type: Application
    Filed: March 14, 2019
    Publication date: October 3, 2019
    Inventors: I-Fen Shih, Yun-Chun Lai, Chien-Chung Chen, Chun-Chen Chen, Yu-Lin Wu
  • Publication number: 20190305104
    Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: International Business Machines Corporation
    Inventors: Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita
  • Publication number: 20190306488
    Abstract: Various examples with respect to method and apparatus for active stereo vision are described. An apparatus may include an electromagnetic (EM) wave emitter, a first sensor and a second sensor. During operation, the EM wave emitter emits EM waves toward a scene, the first sensor captures a first image of the scene in an infrared (IR) spectrum, and the second sensor captures a second image of the scene in a light spectrum. The first image and second image, when processed, may enable active stereo vision.
    Type: Application
    Filed: March 20, 2019
    Publication date: October 3, 2019
    Inventors: Han-Yang Wang, Yu-Chun Chen, Po-Hao Huang, Chao-Chung Cheng, Ying-Jui Chen, Te-Hao Chang
  • Publication number: 20190304990
    Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
    Type: Application
    Filed: March 4, 2019
    Publication date: October 3, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon KIM, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • Patent number: 10431682
    Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Publication number: 20190297138
    Abstract: Optimizing receive side scaling (RSS) key selection is provided. Different weights are assigned to different fields of flow data corresponding to a network connection of a registered client device. A score is generated representing an amount of balanced processor loading for each RSS key corresponding to the registered client device based on the different fields of the flow data with assigned weights. A current RSS key on the registered client device is updated with an optimal RSS key based on the score corresponding to the optimal RSS key representing balanced loading of processors on the registered client device.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 26, 2019
    Inventors: Chih-Wen Chao, Wei-Hsiang Hsiung, Kuo-Chun Chen, Ming-Pin Hsueh, Sheng-Tung Hsu
  • Patent number: 10423255
    Abstract: A touch control display panel includes: pixel units arranged in an array; data lines, any one of which being electrically connected to one column of pixel units; touch wires, arranged in a same layer as the data lines, a distance from the data line of an odd column of pixel units to a touch wire being equal to a distance from the data line of an even column of pixel units to another adjacent touch wire; scan lines, having a quantity of rows same as that of the pixel units; pixel electrodes and common electrodes, the common electrodes being also used as touch electrodes, the pixel electrodes being electrically connected to the pixel units, the touch electrodes being electrically connected to the touch wires. One touch electrode corresponds to multiple pixel electrodes. Therefore, manufacturing process is simplified, production efficiency is improved and thickness of touch control display panel is reduced.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Chung-Chun Chen
  • Publication number: 20190287976
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Application
    Filed: April 23, 2018
    Publication date: September 19, 2019
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Publication number: 20190286885
    Abstract: A face identification system for a mobile device includes a housing and a central processing unit within the housing, the central processing unit configured to unlock or not unlock the mobile device according to a comparison result. The face identification system is disposed within the housing. The face identification system includes a 3D structured light emitting device configured to emit a three-dimensional structured light signal to an object external to the housing. A first neural network processing unit outputs a comparison result to the central processing unit according to processing of an inputted sampled signal. A sensor is configured to perform three-dimensional sampling of the three-dimensional structured light signal as reflected by the object and input the sampled signal directly to the first neural network processing unit.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 19, 2019
    Inventor: Chun-Chen Liu