Abstract: A method related to legalize mixed-cell height standard cells of an IC is provided. A global placement of the IC is obtained. A plurality of standard cells of the IC are placed in the global placement. Each standard cell is moved from a position to the nearest row in the global placement. A displacement value of each moved standard cell is obtained in the global placement. The global placement of the IC is divided into a plurality of windows according to the displacement values of the moved standard cells in each window and a dead space corresponding to each moved standard cell in each window. All overlapping areas among the standard cells of each window are removed to obtain a detailed placement. The IC is manufactured according to the detailed placement. The standard cells have different cell heights in each window.

Abstract: A substrate structure for a vertically stacked transistor includes a substrate having at least one fin and a cavity formed through a portion of the substrate. An inner spacer disposed in the cavity. A first epitaxy layer disposed upon the substrate, and a liner is disposed on portions of the first epitaxy layer and the inner spacer. A second epitaxy layer is disposed upon a top portion of the liner. The first epitaxy layer and the second epitaxy layer share a common U-shaped fin body formed by the inner spacer and the at least one fin.

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

Abstract: A low-power face identification method includes emitting at least one first light signal to an object, receiving at least one second light signal reflected by the object, decoding the at least one second light signal to generate a decoded light signal, extracting two-dimensional image information from the decoded light signal, performing a two-dimensional face detection function by an artificial intelligence chip according to the two-dimensional image information and two-dimensional face training data, inhibiting a two-dimensional face recognition function when a two-dimensional face is undetected, and disabling an image converter by the artificial intelligence chip in order to inhibit a three-dimensional face recognition function when the two-dimensional face recognition function is inhibited.

Abstract: Example systems relate to wireless head-mounted devices. A wireless head-mounted device may include high-throughput performance miming at millimeter wave band receiving hardware to receive a transmission from corresponding high-powered transmitting hardware included in a computing device. The transmission may include audio, visual, or video data. The wireless head-mounted device may further include a plurality of sensors to collect sensor data. The wireless head-mounted device may further include low-powered transmitting hardware to transmit at least the sensor data collected by the sensors to corresponding low-powered receiving software included in the computing device.

Abstract: A voltage regulator apparatus includes operational amplifier, first resistor, second resistor, driving transistor, amplifier circuit, and output circuit. The operational amplifier has first input terminal coupled to reference voltage, second input terminal, and output terminal. The first resistor has first terminal coupled to second input terminal. The second resistor is coupled between first resistor and ground level. The driving transistor has control terminal coupled to output terminal of operational amplifier and first terminal coupled to second terminal of first resistor. The amplifier circuit is coupled to output terminal of operational amplifier and configured to sense output voltage of voltage regulator apparatus to amplify the sensed voltage with specific gain to regulate a transistor of output circuit. The transistor has control terminal controlled by amplifier circuit. The output voltage is generated at first terminal of the transistor.

Abstract: A vestibular system examination device includes a platform unit and an examination unit. The platform unit includes abase, a driving mechanism mounted to the base, and a seat mounted to the driving mechanism and adapted for a user to sit thereon. The seat is driven movably and rotatably with six degrees of freedom by the driving mechanism. The examining unit includes a detector adapted for detecting eye movement or electrooculography of the user, a measuring module electrically connected to the platform unit for measuring location and displacement thereof, and a processing module electrically connected to the detector and the measuring module for receiving and processing data acquired from the detector and the measuring module.

Abstract: A computer-implemented method includes identifying a primary login platform and identifying one or more security developments associated with the primary login platform. The computer-implemented method further includes determining one or more security corrective actions based on the one or more security developments. A corresponding computer program product and computer system are also disclosed.

Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.

Abstract: A computer network endpoint is secured to prevent information leak or other compromise by instantiating in memory first, second and third security zones. With respect to an authorized user, the first zone is readable and writable, the second zone is read-only, and the third zone is neither readable nor writable. System information (e.g., applications, libraries, policies, etc.) are deployed into the first zone from the second zone. When sensitive data is generated in the first zone, e.g., when a secure communication session is established using a cryptographic key, the sensitive data is transferred from the first zone to the third zone, wherein it is immune from information leak or other compromise. The sensitive information is transferable from the third zone to one or more external having a need to know that information. Because information does not pass directly from the first security zone to the external systems, the endpoint is secured against information leak or other attack.

Abstract: A face identification system includes a transmitter, a receiver, a database, an artificial intelligence chip, and a main processor. The transmitter is used for emitting at least one first light signal to an object. The receiver is used for receiving at least one second light signal reflected by the object. The database is used for saving training data. The artificial intelligence chip is coupled to the transmitter, the receiver, and the database for identifying a face image from the object according to the at least one second light signal and the training data. The main processor is coupled to the artificial intelligence chip for receiving a face identification signal generated from the artificial intelligence chip.

Abstract: Fabricating a semiconductor device includes receiving a semiconductor structure including a substrate, a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin. A bottom spacer is formed on the substrate in contact with a bottom portion of the fin. A top spacer is formed in contact with a top portion of the fin. A lateral recess is formed in the substrate under the bottom spacer. A first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer are simultaneously grown. The first epitaxy forms a bottom source and drain and the second epitaxy forms a top source and drain.

Abstract: A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET includes a first source/drain region containing first dopants, and the second FinFET includes a second source/drain region containing second dopants. The method further includes selectively controlling a temperature of the second FinFET with respect to a temperature of the first FinFET during an anneal process to activate the first and second dopants such that the second source/drain region is formed having a different electrical resistance with respect to the first source/drain region.

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract: An optical imaging lens includes a first lens element, a second lens element, a third lens element and a fourth lens element. The optical-axis region of the image-side surface of the first lens element is concave, the periphery region of the image-side surface of the second lens element is convex, a third lens has positive refracting power and the optical-axis region of the object-side surface of the fourth lens element is convex. The Abbe number of the first lens element is ?1, the Abbe number of the second lens element is ?2, the Abbe number of the third lens element is ?3 and the Abbe number of the fourth lens element is ?4 to satisfy ?2?30.000 and ?1+?3+?4?120.000.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.

Abstract: A semiconductor structure. The structure includes first source/drain located in a first source/drain region. The structure includes a second source/drain located in a second source/drain region. The structure includes a plurality of semiconductor nanosheets located between the first source/drain and the second source/drain in a gate region. The structure includes an insulating layer separating the first source drain from a bulk substrate. The bulk substrate may have a first horizontal surface in the gate region, a second horizontal surface in the first source/drain region, and a connecting surface forming an at least partially vertical connection between the first horizontal surface and the second horizontal surface. The insulating layer may be directly on the second horizontal surface and the connecting surface.