Patents by Inventor An Chung

An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194655
    Abstract: A display apparatus includes a display substrate, and light emitting devices arranged on an upper surface of the display substrate. At least one of the light emitting devices includes a first LED unit including a first light emitting stack, a second LED unit including a second light emitting stack, and a third LED unit including a third light emitting stack. The second LED unit is disposed between the first LED unit and the third LED unit. Each of the first to third light emitting stacks includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer in each of the first to third light emitting stacks are stacked in a horizontal direction with respect to the upper surface of the display substrate.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 13, 2024
    Inventors: Chung Hoon LEE, So Ra LEE
  • Publication number: 20240196544
    Abstract: A process method for laser removal of substrate solder mask by: providing a substrate with solder pads; covering the substrate and the solder pads with a solder mask, where the part of the solder mask facing the substrate is the shielding part and the part of the solder mask facing the solder pads is the clearing part; using a camera module to read the QR-code for plate production part number on the substrate; automatically importing the CAD/CAM data to the laser device, where the CAD/CAM data corresponds to the plate production part number; sequentially stripping the cleaning part through the laser beam according to the CAD/CAM data to make the solder mask form a hollow portion; taking a picture of the substrate and taking out the processed substrate picture; completing the substrate processing job if the processed substrate picture and the CAD/CAM data are the same.
    Type: Application
    Filed: December 7, 2022
    Publication date: June 13, 2024
    Inventor: Pei-Chung PANG
  • Publication number: 20240195945
    Abstract: A method for automatically detecting a projector configuration and a projection system are provided. First, multiple projectors are searched in a network domain, and each projector is correspondingly equipped with an imaging apparatus. Next, the projectors are driven to project, and the imaging apparatuses are driven to capture images. Afterwards, the projectors are grouped based on one or more projected ranges comprised in an imaging range of the imaging apparatus corresponding to each projector. A configuration relationship of the projected ranges of the projectors in the same group is determined for overlapping areas between the projected ranges of the projectors grouped in the same group. The method for automatically detecting the projector configuration and the projection system proposed by the disclosure can automatically detect the actual configuration relationship of the projectors.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Applicant: Coretronic Corporation
    Inventors: Chun-Lin Chien, Chung-Lung Yang, Yu-Wen Lo, Xuan-En Fung
  • Publication number: 20240196595
    Abstract: The present application provides a memory device having an ultra-lightly doped region and a manufacturing method of the memory device. The memory device includes a semiconductor substrate including a word line extending into the semiconductor substrate, wherein the semiconductor substrate is defined with a source region, a drain region and an ultra-lightly doped region under the drain region, the word line is disposed between the source region and the drain region, and the ultra-lightly doped region is disposed at a sidewall of the word line.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Inventor: CHUNG-LIN HUANG
  • Patent number: 12009328
    Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: June 11, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsoo Chung, Taewon Yoo, Myungkee Chung
  • Patent number: 12008949
    Abstract: The present application provides a driver for a display panel, the driver comprises at least one driving circuit, generating a plurality of Type-1 driving signals and a plurality of Type-2 driving signals for driving a plurality of pixels on display panel. The pixels include a plurality of first pixels and a plurality of second pixels adjacent to the first pixels. Each pixel includes a first display element, a second display element, a third display element. The Type-1 driving signals drive the first, second, and third display elements of the first pixels. The Type-2 driving signals drive the first, second, and third display elements of the second pixels. A first pulse of the Type-1 driving signals and a second pulse of the Type-2 driving signals are located at different time segments. By adopting the driver according to the present application, current concentration may be avoided and displaying quality may be improved.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: June 11, 2024
    Assignee: SITRONIX TECHNOLOGY CORP.
    Inventor: Chung-Hsin Su
  • Patent number: 12008302
    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang, Yung-Chin Hou
  • Patent number: 12005532
    Abstract: Systems, methods, and apparatuses of a welding system are disclosed and include a first stage of a scanning device for scanning weld parts to generate a three-dimensional (3D) profile of a weld target wherein the 3D profile captures matching imperfections of a meeting together of the set of weld parts when performing the weld operation; and the second stage of a monitoring device to monitor the weld operation and to generate a data of high-resolution measurements of the weld operation; wherein the first stage further includes the monitoring device determining a weld schedule based on the 3D profile, and to adjust the weld schedule while the weld operation progresses to adapt to predicted distortion based on the 3D profile and to sensed distortion; wherein the second stage further includes a plurality of sensors to sense a set of components associated with the weld operation to generate high-resolution data of measurements.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: June 11, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Debejyo Chakraborty, Miguel Arturo Saez, John Patrick Spicer, Pei-chung Wang, Spyros P Mellas, Wayne Cai, James M Ward
  • Patent number: 12008183
    Abstract: The disclosure provides a display panel including a substrate, an active layer, a first electrode layer, a common electrode layer, a cathode layer, and a spacer. The active layer is located on the substrate. The first electrode layer is located on the active layer, and the first electrode layer includes a first gate and a second gate. The common electrode layer is located on the first electrode layer. The common electrode layer has a first region, a second region, and a first necking region. The first necking region connects the first region and the second region. The first region and the first gate are correspondingly disposed, and the second region and the second gate are correspondingly disposed. The cathode layer is located on the common electrode layer. The spacer is located between the common electrode layer and the cathode layer. The spacer and the first necking region are correspondingly disposed.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: June 11, 2024
    Assignee: Innolux Corporation
    Inventors: Chung-Wen Yen, Hsia-Ching Chu, Kuan-Feng Lee, Yu-Sheng Tsai
  • Patent number: 12008906
    Abstract: A method of blind spot detection is provided. The method of blind spot detection is used for a vehicle including a first vehicle body and a second vehicle body dragged by the first vehicle body. The method of blind spot detection comprises the following steps: obtaining a turning angle information of the second vehicle body relative to the first vehicle body by a first sensor while the vehicle is moving; determining a predetermined information related to the vehicle and/or a second sensor; dynamically defining a blind spot area around the vehicle according to the turning angle information and the predetermined information; and receiving a sensing signal regarding an object around the vehicle from the second sensor to determine whether the object is located in the blind spot area.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: June 11, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Lien Ho, Wei-Kuo Chen
  • Patent number: 12005612
    Abstract: Disclosed is a method of manufacturing a transparent stretchable substrate according to various embodiments of the present disclosure. The method may include generating a substrate part formed of an elastic material, generating an auxetic including a plurality of unit structures on the substrate part, and generating a fixing part on the substrate part on which the auxetic is generated.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: June 11, 2024
    Assignee: Korea Institute of Science and Technology
    Inventors: Seungjun Chung, Phillip Lee, Seung Hyun Lee, Seong Kwon Hwang, Hyunjoo Cho, Jeong Gon Son, Jai Kyeong Kim, Heesuk Kim, Sang-Soo Lee, Tae Ann Kim, Jong Hyuk Park
  • Patent number: 12008242
    Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chung Chen, Ming-Chien Huang
  • Patent number: 12009329
    Abstract: A semiconductor manufacturing method includes forming a first redistribution structure with a fine redistribution circuitry over a first temporary carrier; forming testing tips on a first surface of the fine redistribution circuitry; transferring the testing tips and the first redistribution structure to a second temporary carrier provided with a temporary adhesive layer, where the testing tips are embedded in the temporary adhesive layer with the second temporary carrier disposed on the temporary adhesive layer; releasing the first temporary carrier to expose a second surface of the fine redistribution circuitry; coupling a second redistribution structure with a coarse redistribution circuitry to the first redistribution structure through conductive joints, where the conductive joints are formed on the second surface of the fine redistribution circuitry; and releasing the second temporary carrier and the temporary adhesive layer from the testing tips and the first redistribution structure after coupling the
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 11, 2024
    Inventor: Dyi-Chung Hu
  • Patent number: 12009403
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a fin protruding from a substrate and a gate stack formed across the fin. The semiconductor structure further includes a source/drain structure attaching to the gate stack and a contact structure connecting to the source/drain structure. The semiconductor structure further includes a first cap layer covering a top surface of the contact structure. In addition, the first cap layer includes a first halogen.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 12005545
    Abstract: The embodiments of the present application provide a fixing device and a detection system. The fixing device includes: a bearing disk used for bearing a lapping head, the bearing disk being provided with positioning holes and a first positioning ring, the positioning holes being used for accommodating and fixing a positioning pin of a first type of lapping head, and the first positioning ring being used for fixing a positioning disk of a second type of lapping head.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: June 11, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Chao Li, Chin-Chung Ku
  • Patent number: 12007280
    Abstract: Systems, apparatuses, and methods for multi-application optical sensing are provided. For example, an optical sensing apparatus can include a photodetector array, a first circuitry, and a second circuitry. The photodetector array includes a plurality of photodetectors, wherein a first subset of the plurality of photodetectors are configured as a first region for detecting a first optical signal, and a second subset of the plurality of photodetectors are configured as a second region for detecting a second optical signal. The first circuitry, coupled to the first region, is configured to perform a first function based on the first optical signal to output a first output result. The second circuitry, coupled to the second region, is configured to perform a second function based on the second optical signal to output a second output result.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: June 11, 2024
    Assignee: ARTILUX, INC.
    Inventors: Chih-Wei Yeh, Hung-Chih Chang, Yun-Chung Na, Tsung-Ting Wu, Shu-Lu Chen
  • Patent number: 12009384
    Abstract: A light emitting diode (LED) stack for a display including a substrate, a first LED stack disposed on the substrate, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, a first color filter interposed between the first LED stack and the second LED stack, and a second color filter interposed between the second LED stack and the third LED stack, in which the second LED stack and the third LED stack are configured to transmit light generated from the first LED stack to the outside, and the third LED stack is configured to transmit light generated from the second LED stack to the outside.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: June 11, 2024
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Chang Yeon Kim, Ho Joon Lee
  • Patent number: 12010930
    Abstract: A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 11, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Hsueh-Chung Chen, Mary Claire Silvestre, Yann Mignot
  • Patent number: 12005711
    Abstract: The method of the present disclosure includes steps of: (S1) providing a silicon substrate; (S2) arranging and disposing an active component layer by utilizing a first type photomask on at least two high-precision regions of each of a plurality of inkjet print head chip regions on the silicon substrate; (S3) arranging and disposing a passive component layer by utilizing a second type photomask on the active component layer; and (S4) cutting the silicon substrate according to the inkjet print head chip regions so as to form the plurality of narrow type inkjet print head chips.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 11, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han
  • Patent number: D1030591
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: June 11, 2024
    Assignee: Dr. Ing. h.c. F. Porsche Aktiengesellschaft
    Inventor: Woosung Chung