Abstract: A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: A semiconductor device includes a patterned wiring layer disposed above a semiconductor substrate, the patterned wiring layer including a plurality of wiring portions, and adjacent wiring portions being separated from each other. The semiconductor device also includes a first insulating passivation layer disposed over the wiring portions in a region between adjacent wiring portions, the first insulating passivation layer having a horizontal surface in the region between adjacent wiring portions. The semiconductor device further includes a second insulating passivation layer disposed on the first insulating passivation layer. The first insulating passivation layer and the second insulating passivation layer do not have a void in the region between adjacent wiring lines.

Abstract: A semiconductor device may include one or more low dielectric constant (low-?) layers on a substrate. The semiconductor device may include a dielectric layer on the one or more low-? layers. The semiconductor device may include a structure through the substrate, the one or more low-? layers, and the dielectric layer. The semiconductor device may include a liner layer between the structure and the substrate, between the structure and the one or more low-? layers, and between the structure and the dielectric layer. The semiconductor device may include a capping layer between the liner layer and the dielectric layer and between the liner layer and the one or more low-? layers.

Abstract: A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.

Abstract: A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

Abstract: A diaphragm position of a valve may be detected and/or determined such that operation of the diaphragm may be monitored. A sensor included in the valve may generate sensor data that may be used to monitor the position of the diaphragm, which in turn may be used to determine a flow of a fluid through the valve. In this way, the sensor may be used to determine whether the diaphragm is properly functioning, may be used to identify and detect failures of the diaphragm, and/or may be used to quickly terminate operation of an associated deposition tool. This may reduce semiconductor substrate scrap, may reduce device failures on semiconductor substrates that are processed by the deposition tool, may increase semiconductor processing quality of the deposition tool, and/or may increase semiconductor processing yields of the deposition tool.

Abstract: Embodiments include a method and device resulting from the method, including using a radical oxidation process to oxidize a spacer layer which lines the opening after removing a dummy gate electrode. The oxidized layer is removed by an etching process. An STI region disposed below the dummy gate electrode may be partially etched.

Abstract: The present disclosure relates to systems and methods for reducing the humidity within a FOUP (Front Opening Unified Pod) when loaded on an EFEM (Equipment Front End Module) for transfer of a semiconductor wafer substrate during fabrication processes. A deflector of specified structure is placed inside the EFEM above the load port of the FOUP. The deflector directs airflow in the EFEM away from the load port. The deflector includes a body with a plurality of apertures in the deflector body, and with a sloped front surface. Thus, the degree of penetration of high-humidity air from the EFEM into the FOUP is reduced.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

Abstract: A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

Abstract: A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

Abstract: A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.

Abstract: A semiconductor device may include one or more low dielectric constant (low-?) layers on a substrate. The semiconductor device may include a dielectric layer on the one or more low-? layers. The semiconductor device may include a structure through the substrate, the one or more low-? layers, and the dielectric layer. The semiconductor device may include a liner layer between the structure and the substrate, between the structure and the one or more low-? layers, and between the structure and the dielectric layer. The semiconductor device may include a capping layer between the liner layer and the dielectric layer and between the liner layer and the one or more low-? layers.

Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Abstract: The present disclosure relates to systems and methods for reducing the humidity within a FOUP (Front Opening Unified Pod) when loaded on an EFEM (Equipment Front End Module) for transfer of a semiconductor wafer substrate during fabrication processes. A deflector of specified structure is placed inside the EFEM above the load port of the FOUP. The deflector directs airflow in the EFEM away from the load port. The deflector includes a body with a plurality of apertures in the deflector body, and with a sloped front surface. Thus, the degree of penetration of high-humidity air from the EFEM into the FOUP is reduced.