Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract: A high aspect ratio structure is provided. The high aspect ratio structure includes a substrate, a plurality of stack structures, and a plurality of support structures. The stack structures are disposed on the substrate, and a trench is formed between adjacent two stack structures. Each of the stack structures includes a plurality of first material layers and a plurality of second material layers. The second material layers and the first material layers are disposed alternately. The support structures are respectively disposed between the substrate and the stack structures, wherein each of the support structures has a concave-convex surface.

Abstract: Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

Abstract: A semi-damascene method is described for fabricating wordlines without stringers while maintaining critical cell dimensions when wordline pitch is less than 40 nm. A thin conducting layer protects a storage layer during manufacture, the thin conducting layer then making contact with filled-in conducting material.

Abstract: High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Abstract: A semiconductor stack includes a carbon doped/implanted stop layer that reacts with etching plasma to form polymers that maintain bottom etched critical dimension (ECD) and avoid excess recess depth when over-etching in high-aspect-ratio structures.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract: A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench.

Abstract: A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the dielectric material, etching the dielectric material until the bottom liner layer is exposed, forming a protective layer on a sidewall of the spacer while etching the dielectric material, and etching the bottom liner layer.

Abstract: A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench.

Abstract: A method of forming a plurality of self-aligned contacts of a core region and local interconnect openings of a peripheral region of a semiconductor device is disclosed. A plurality of gate-structures are formed on the core and peripheral regions of a semiconductor substrate. Sidewall spacers then are formed around the gate structures. A liner layer and a dielectric layer are sequentially formed on the semiconductor substrate. Then a photoresist pattern is formed to define a plurality of self-aligned contacts of said core region and local interconnect openings of the peripheral region, and the dielectric layer, liner layer and sidewall spacers are etched to form a plurality of self-aligned contacts of the core region and local interconnect contacts of the peripheral region. This is achieved by an etching step having a high selectivity with respect to the dielectric layer and sidewall spacers.

Abstract: Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching.

Abstract: Methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; and etching the substrate, wherein the introduction of the N2 gas is stopped prior to etching, and wherein etching comprises an initial plasma ignition wherein at least a portion of the N2 gas remains present in the chamber during initial plasma ignition. Additional methods are described which comprise: providing a plasma etching apparatus having an etching chamber; disposing a substrate to be etched in the chamber; introducing N2 gas and one or more process gases into the chamber; applying power to an electrode in the chamber such that an N2 memory species is formed; and etching the substrate, where the introduction of the N2 gas into the chamber can be stopped prior to etching.

Abstract: A method of forming a plurality of self-aligned contacts of a drain region and local interconnect openings of a source region of a semiconductor device is disclosed. A plurality of gate-structures are formed on the drain and source regions of a semiconductor substrate. Sidewall spacers then are formed around the gate structures. A liner layer and a dielectric layer are sequentially formed on the semiconductor substrate. Then a photoresist pattern is formed to define a plurality of self-aligned contacts of said drain region and local interconnect openings of the source region, and the dielectric layer, liner layer and sidewall spacers are etched to form a plurality of self-aligned contacts of the drain region and local interconnect contacts of the source region. This is achieved by an etching step having a high selectivity with respect to the dielectric layer and sidewall spacers.