Abstract: A method for manufacturing a CIS reduces or prevents dark current in a photodiode region. In the method, a plurality of gates are formed on a semiconductor substrate, and impurities are implanted in side portions of a predetermined gate to form a photodiode region. Subsequently, a spacer nitride layer is formed and then etched to form a first spacer pattern covering the photodiode region and a second spacer pattern on sidewalls of the rest of the gates. After that, impurities are implanted using the first and second spacer patterns as a mask to form source/drain regions in portions of the semiconductor substrate that are exposed at the side portions of the gate(s). Subsequently, a salicide is formed on the gate and in the exposed portion of the semiconductor substrate.

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Abstract: An inner suspension system for a speaker assembly comprising a center spider, an intermediate spider, and a linear spider. The system reduces distortion of the output from the speaker and increases axial integrity of the movement of the cone. The center spider and intermediate spider are disk shaped and are each attached to the frame of the speaker assembly and to different points on the voice coil former. The linear spider, on the other hand, is cylindrically shaped and is attached to the pole piece of the magnetic motor structure, and the cone converges upon the other end of the cylindrically shaped linear spider.