Abstract: The present disclosure discloses a method for improving the performance of concrete aggregates, comprising the following steps: (1) adding composite microbial powders, recycled aggregates and water into a stirring pot in a certain ratio to be continuously and uniformly stirred; (2) placing the recycled aggregate obtained in step (1) and another microbial powder in a vacuum device so as to fill the microbial powder into the cracks of the recycled aggregate in a negative-pressure environment; and (3) spraying a calcium source solution to the surface of the recycled aggregate obtained in step (2) at an interval of 5-6 hours for repeating 3-5 times to maintain the wet surface of the recycled aggregate.

Abstract: A method includes positioning an end effector at a height lower than a height of a wafer. The end effector is moved to a position under the wafer. A wafer backside property of the wafer is detected by using a sensor on the end effector. The wafer backside property is analyzed to obtain an analysis result.

Abstract: A foldable light-shielding hood includes a plate body, a first supporting portion, a second supporting portion, a hanging portion, a first folded portion, and a second folded portion. The first supporting portion, the second supporting portion, and the hanging portion are foldably disposed to the plate body. The first folded portion is foldably disposed to the first supporting portion. The second folded portion is foldably disposed to the second supporting portion. The foldable light-shielding hood is adapted for hanging on a portable electronic device through the hanging portion. The first folded portion, the second folded portion, the hanging portion, the first supporting portion, the second supporting portion, and the plate body surround a shielding space, and the first folded portion, the second folded portion, and the hanging portion are adapted for being combined with the portable electronic device, and a display surface is located in the shielding space.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A display device control method includes when an operation on an on-screen display (OSD) input device is received, determining whether a signal generated by operating the OSD input device is currently sent to an OSD system or an operating system (OS); and when the signal generated by operating the OSD input device is currently sent to the OS-system, switching, according to a control signal generated by the OSD input device, the control signal from being sent to the OSD system to being sent to the OS-system. This application further provides a display device.

Abstract: A method for quality assurance may include obtaining a state of a medical device. The method may also include obtaining a target plan of a target subject. The method may also include determining a prediction result based on the state of the medical device and the target plan of the target subject. The method may also include determining whether a quality assurance test passes based on the prediction result.

Abstract: A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.

Abstract: Provided herein is a system and method to determine a heading of a target. The system includes a radar sensor that obtains a snapshot of radar data comprising Doppler velocities and spatial positions of a plurality of detection points of a target, one or more processors, and a memory storing instructions that, when executed by the one or more processors, causes the system to perform conducting a first estimation of a heading of the target based on the spatial positions; conducting a second estimation of the heading of the target based on the Doppler velocities; and obtaining a combined estimation of the heading of the target based on a weighted sum of the first estimation and the second estimation.

Abstract: A method for adjusting a transmitting (TX) power ratio of a radio module includes: separating multiple radio modules into multiple radio groups according to a radiofrequency (RF) regulation, wherein the multiple radio modules comprise the radio module; mapping an RF exposure limit to a TX power limit; interacting with at least one other radio module for adjusting the TX power ratio, to obtain at least one adjusted TX power ratio, wherein the radio module and the at least one other radio module are comprised in a same radio group of the multiple radio groups; and adjusting the TX power limit according to the at least one adjusted TX power ratio, to generate an adjusted TX power limit of the radio module.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

Abstract: The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers, two epitaxial structures, a conductive structure, a via, and a graphene barrier. The channel layers and the epitaxial structures are disposed over the substrate. The channel layers are connected between the epitaxial structures. The conductive structure is disposed on the substrate opposite to the epitaxial structures. The via is connected between one of the epitaxial structure and the conductive structure. The graphene barrier surrounds the via.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

Abstract: The present disclosure may provide a composite decoration board and a manufacturing method thereof. The composite decoration board may include a substrate layer. The substrate layer may include at least one first structural layer and a second structural layer. The at least one first structural layer may be connected to the second structural layer up and down. Ingredients of at least one first structural layer or the second structural layer may include poly(ethylene terephthalateco-1,4-cyclohexylenedimethylene terephthalate) (PETG) resin. A weight of the PETG resin of each first structural layer in the at least one first structural layer may be greater than a weight of the PETG resin of the second structural layer.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a memory cell on the semiconductor substrate, where the memory cell includes a bottom contact, a memory material on the bottom contact, a top contact on the memory material, a first electrical isolation structure laterally surrounding the top contact, and a second electrical isolation structure laterally surrounding the memory material and the bottom contact.

Abstract: A light-splitting reflection high-concentration photovoltaic photothermal integrated cavity receiver includes a photothermal assembly and a photovoltaic assembly. The photothermal assembly includes a high-temperature heat storage system, a low-temperature heat storage system, a plurality of heat exchange tube bundles defining a reflective cavity, and an ultraviolet and visible light reflective film arranged on an inner surface of the reflective cavity. The plurality of heat exchange tube bundles are communicated to form a heat collection circuit, and the heat collection circuit has an input end connected with the low-temperature heat storage system, and an output end connected with the high-temperature heat storage system. The photovoltaic assembly is arranged at a focus of the reflective cavity, and includes a near-infrared reflective film, a high concentration photovoltaic integrated receiver and a concentration photovoltaic cooler stacked sequentially along an incident direction of light.