Patents by Inventor An-Hong Liu
An-Hong Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9307676Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.Type: GrantFiled: July 5, 2013Date of Patent: April 5, 2016Assignee: CHIPMOS TECHNOLOGIES INC.Inventors: Tzu Hsin Huang, Yu Ting Yang, Hung Hsin Liu, An Hong Liu, Geng Shin Shen, David Wei Wang, Shih Fu Lee
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Publication number: 20130294033Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.Type: ApplicationFiled: July 5, 2013Publication date: November 7, 2013Inventors: TZU HSIN HUANG, YU TING YANG, HUNG HSIN LIU, AN HONG LIU, GENG SHIN SHEN, DAVID WEI WANG, SHIH FU LEE
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Patent number: 8564954Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.Type: GrantFiled: November 18, 2010Date of Patent: October 22, 2013Assignee: Chipmos Technologies Inc.Inventors: Tzu Hsin Huang, Yu Ting Yang, Hung Hsin Liu, An Hong Liu, Geng Shin Shen, Wei David Wang, Shih Fu Lee
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Patent number: 8550345Abstract: This invention provides an RFID real-time information system accommodated to a semiconductor supply chain for exchanging real-time information. The RFID real-time information system is characterized by comprising an RFID middleware module for generating a stock and logistic information corresponding to a plurality of carriers and wafers from a tag information; a manufacturing information module for storing an object information corresponding to the plurality of wafers; a real-time information module for integrating the RFID middleware module with the manufacturing information module to generate real-time information corresponding to the plurality of wafers and carriers; and a business-to-business (B2B) e-commerce module comprising a plurality of B2B servers respectively disposed in vendors in the semiconductor supply chain for connecting and exchanging the real-time information through a standard protocol of e-commerce.Type: GrantFiled: May 15, 2008Date of Patent: October 8, 2013Assignee: Chipmos Technologies Inc.Inventors: Cheng-Fang Huang, Pin-Hsun Huang, Chih-Hsiang Wang, Wen-Cheng Hsu, Yi-fang cho, An-Hong Liu, Yi-Chang Lee
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Publication number: 20130119530Abstract: A thermally enhanced packaging structure includes a chip carrier; a high power chip disposed on the chip carrier; a molding compound covering the high power chip; a heat dissipating layer disposed on the molding compound, wherein the heat dissipating layer comprises a plurality of carbon nanocapsules (CNCs); and a non-fin type heat dissipating device, disposed either on the heat dissipating layer or between the molding compound and the heat dissipating layer. The molding compound can also comprise a plurality of CNCs.Type: ApplicationFiled: August 17, 2012Publication date: May 16, 2013Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: AN HONG LIU, David Wei Wang, Shi Fen Huang, Yi Chang Lee, Hsiang Ming Huang
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Publication number: 20130069228Abstract: A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate.Type: ApplicationFiled: July 26, 2012Publication date: March 21, 2013Inventors: An-Hong LIU, Hung-Hsin Liu, Jar-Dar Yang, Chi-Chia Huang, Yi-Chang Lee, Hsiang-Ming Huang
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Publication number: 20130049787Abstract: The present invention provides a method of testing a stacked semiconductor device structure. This method includes the following steps: providing a testing board having a plurality of testing points and a probe card; providing a substrate which is disposed on the testing board; providing a plurality of semiconductor devices; mounting and electrically connecting a first one of the semiconductor devices onto the substrate; mounting and electrically connecting a second one of the semiconductor devices onto the first one of the semiconductor devices; keeping the probe card in contact with the second one of the semiconductor devices for electrical testing; and repeating the steps of mounting and testing of the semiconductor devices until all of the semiconductor devices are tested. This method can ensure the integrity of electrical interconnections between the semiconductor devices of the stacked structure.Type: ApplicationFiled: April 12, 2012Publication date: February 28, 2013Inventors: Chi-Ming YI, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
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Patent number: 8338935Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.Type: GrantFiled: May 26, 2011Date of Patent: December 25, 2012Assignee: Chipmos Technologies Inc.Inventors: An Hong Liu, David Wei Wang
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Publication number: 20120299036Abstract: A thermally enhanced light emitting device package includes a substrate, a chip attached to the substrate, an encapsulant overlaid on the chip, and a plurality of non-electrically conductive carbon nanocapsules mixed in the encapsulant to facilitate heat dissipation from the chip.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: AN HONG LIU, RUENN BO TSAI, DAVID WEI WANG
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Patent number: 8269352Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: GrantFiled: January 12, 2011Date of Patent: September 18, 2012Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Patent number: 8269351Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: GrantFiled: January 12, 2011Date of Patent: September 18, 2012Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Patent number: 8264068Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: GrantFiled: January 12, 2011Date of Patent: September 11, 2012Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110309496Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: ApplicationFiled: January 12, 2011Publication date: December 22, 2011Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110309497Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: ApplicationFiled: January 12, 2011Publication date: December 22, 2011Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110309495Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.Type: ApplicationFiled: January 12, 2011Publication date: December 22, 2011Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Jar-Dar Yang, Yi-Chang Lee
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Publication number: 20110304045Abstract: A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate.Type: ApplicationFiled: May 26, 2011Publication date: December 15, 2011Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: AN HONG LIU, DAVID WEI WANG
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Publication number: 20110304991Abstract: A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.Type: ApplicationFiled: November 18, 2010Publication date: December 15, 2011Applicant: CHIPMOS TECHNOLOGIES INC.Inventors: TZU HSIN HUANG, YU TING YANG, HUNG HSIN LIU, AN HONG LIU, GENG SHIN SHEN, DAVID WEI WANG, SHIH FU LEE
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Publication number: 20110291267Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.Type: ApplicationFiled: August 16, 2010Publication date: December 1, 2011Inventors: David Wei Wang, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
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Publication number: 20110291268Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.Type: ApplicationFiled: August 16, 2010Publication date: December 1, 2011Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
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Patent number: 7973310Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.Type: GrantFiled: July 10, 2009Date of Patent: July 5, 2011Assignee: Chipmos Technologies Inc.Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho