Patents by Inventor An Hsieh

An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100082883
    Abstract: A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table.
    Type: Application
    Filed: February 26, 2009
    Publication date: April 1, 2010
    Inventors: Ming-Dar Chen, Tso-Cheng Su, Shih-Fang Hung, Tzu-Wei Fang, Hsiang-An Hsieh
  • Patent number: 7685359
    Abstract: A method of setting a storage device that a storage management program is built in an application system is used to set a disk label of the storage device and without specially developed application program is set between the application system and the storage device. Some command codes are set as default in the storage device to detect whether the disk label of the storage device is set by the application system includes command codes or not to execute operations are set by the command codes so as to operate the storage device.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: March 23, 2010
    Assignee: Carry Computer Eng. Co., Ltd.
    Inventor: Hsiang-An Hsieh
  • Patent number: 7679451
    Abstract: A power supply device for driving an amplifier includes a power generator for providing a first voltage for a first power reception end of the amplifier, a power conversion unit coupled to the power generator, for converting the first voltage into a second voltage, a charge pump coupled between the power conversion unit and a second power reception end of the amplifier, for generating a third voltage for the amplifier according to the second voltage, and a control unit coupled to the power conversion unit, for controlling the power conversion unit, so as to adjust the second voltage to make the third voltage equal to a specific multiple of the first voltage.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: March 16, 2010
    Assignee: Anpec Electronics Corporation
    Inventors: Fu-Yuan Chen, Chung-An Hsieh, Yueh-Ping Yu
  • Publication number: 20100056313
    Abstract: A limited slip differential includes a driving plate, backing plates, differential gear assemblies, and a transmission assembly engaged together inside a sealed casing where fluid is pumped. The driving plate has pairs of communicated openings for interlocking two gears of each gear assembly, which extend by opposite directions from the driving plate for separately engaging with the transmission assembly. While synchronously rotating the plates, the gear assemblies are alternatively soaked into the fluid and each permits the fluid passing among the gears for adjusting the rotational speed. In the event that the rotational speed difference of axle shafts of the vehicle exceeds a threshold value, the LSD applies at least one gear assembly to generate a back pressure and efficiently block the fluid passing through the gears for limiting mutual rotational speed difference, hence achieving a limited-slip effect.
    Type: Application
    Filed: July 9, 2009
    Publication date: March 4, 2010
    Inventors: Kuo-Ming Lee, Yu-An Hsieh
  • Patent number: 7667543
    Abstract: A power supply device for driving first and second amplifiers includes a first power generator, a second power generator, a charge pump and a control unit. The first power generator provides a first voltage for first power reception ends of the first and second amplifiers. The second power generator provides a second voltage. The charge pump is coupled between the second power generator and a second power reception end of the first amplifier and between the second power generator and a second power reception end of the second amplifier, and is used for generating a third voltage for the first and second amplifiers according to the second voltage. The control unit is coupled to the second power generator and is used for controlling the second power generator, so as to adjust the second voltage to make the third voltage equal to a multiple of the first voltage.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: February 23, 2010
    Assignee: Anpec Electronics Corporation
    Inventors: Fu-Yuan Chen, Chung-An Hsieh, Yueh-Ping Yu
  • Publication number: 20100037006
    Abstract: A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks.
    Type: Application
    Filed: July 24, 2009
    Publication date: February 11, 2010
    Applicant: A-DATA TECHNOLOGY (SUZHOU) CO, LTD.
    Inventors: Ming-Dar Chen, Hsiang-An Hsieh, Chuan-Sheng Lin
  • Patent number: 7651937
    Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 26, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
  • Publication number: 20090307537
    Abstract: A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency.
    Type: Application
    Filed: September 11, 2008
    Publication date: December 10, 2009
    Inventors: Ming-Dar Chen, Chuan-Sheng Lin, Hsiang-An Hsieh
  • Publication number: 20090307418
    Abstract: The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.
    Type: Application
    Filed: March 17, 2009
    Publication date: December 10, 2009
    Inventors: Ming-Dar Chen, Chuan-Sheng Lin, Tso-Cheng Su, Shih-Fang Hung, Tzu-Wei Fang, Hsiang-An Hsieh
  • Publication number: 20090300082
    Abstract: A method for memory space management is disclosed. It uses a resident program loaded into an operation system or the controller of a storage device to monitor the storage space and the resource allocation of the file system of the storage device. The status of the logical address with an erased and invalid data mapped with a physical block is checked via a L2P mapping table. By using a data erase instruction, the controller modifies the L2P mapping table to cancel the link relation between the physical block and the logical address and erase the physical block to release the memory space. Finally, the check location is stored for a next check. The method for memory space management improves the access speed and the usage life of the storage device.
    Type: Application
    Filed: November 21, 2008
    Publication date: December 3, 2009
    Inventors: Ming-Dar Chen, Hsiang-An Hsieh
  • Publication number: 20090300273
    Abstract: A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency.
    Type: Application
    Filed: September 24, 2008
    Publication date: December 3, 2009
    Inventors: Ming-Dar Chen, Chuan-Sheng Lin, Hsiang-An Hsieh
  • Publication number: 20090278608
    Abstract: A power supply device for driving an amplifier includes a power generator for providing a first voltage for a first power reception end of the amplifier, a power conversion unit coupled to the power generator, for converting the first voltage into a second voltage, a charge pump coupled between the power conversion unit and a second power reception end of the amplifier, for generating a third voltage for the amplifier according to the second voltage, and a control unit coupled to the power conversion unit, for controlling the power conversion unit, so as to adjust the second voltage to make the third voltage equal to a specific multiple of the first voltage.
    Type: Application
    Filed: April 18, 2008
    Publication date: November 12, 2009
    Inventors: Fu-Yuan Chen, Chung-An Hsieh, Yueh-Ping Yu
  • Publication number: 20090278607
    Abstract: A power supply device for driving first and second amplifiers includes a first power generator, a second power generator, a charge pump and a control unit. The first power generator provides a first voltage for first power reception ends of the first and second amplifiers. The second power generator provides a second voltage. The charge pump is coupled between the second power generator and a second power reception end of the first amplifier and between the second power generator and a second power reception end of the second amplifier, and is used for generating a third voltage for the first and second amplifiers according to the second voltage. The control unit is coupled to the second power generator and is used for controlling the second power generator, so as to adjust the second voltage to make the third voltage equal to a multiple of the first voltage.
    Type: Application
    Filed: April 18, 2008
    Publication date: November 12, 2009
    Inventors: Fu-Yuan Chen, Chung-An Hsieh, Yueh-Ping Yu
  • Publication number: 20090282305
    Abstract: A storage system with a data recovery function and its method reduce errors in a storage medium to a recoverable range of a general ECC function by repeating a testing and recovery procedure for one or more times to assure the accuracy of reading data and enhance the data reliability effectively. The data recovery procedure includes the steps of providing test data by a test data generator of the storage system, writing the test data into a memory block where error data is found, finding an error bit by reading the test data, reducing the error to a recoverable range of the ECC technique by the recovery procedure. If the error bit cannot be found or reduced to a recoverable range of the ECC technique within an upper limit of the number of tests, the memory block is marked as bad.
    Type: Application
    Filed: October 1, 2008
    Publication date: November 12, 2009
    Applicant: A-DATA TECHNOLOGY CO., LTD.
    Inventors: Ming-Dar Chen, Chuan-Sheng Lin, Hsiang-An Hsieh, Hui-Neng Chang
  • Patent number: 7609114
    Abstract: The invention provides a voltage generating apparatus for powering at least one amplifier. The voltage generating apparatus comprises a voltage source, a switched capacitor voltage converter and a voltage detector. The voltage source supplies a first voltage to a positive voltage input terminal of the at least one amplifier. The first voltage is a positive DC voltage. The switched capacitor voltage converter is coupled to the voltage source for outputting an output voltage to a negative voltage input terminal of the at least one amplifier according to the first voltage and a predetermined voltage. The output voltage is a negative DC voltage. The voltage detector is coupled to the switched capacitor voltage converter for determining a switching frequency corresponding to the predetermined voltage according to the output voltage.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 27, 2009
    Assignee: UPI Semiconductor Corporation
    Inventors: Chung-An Hsieh, Cheng-Tao Li
  • Publication number: 20090228601
    Abstract: A method for processing an audio/video bit-stream includes the steps of receiving an input bit-stream, detecting whether the input bit-stream has a startcode emulation prevention pattern, and removing the startcode emulation prevention pattern from the input bit-stream to generate an output bit-stream and setting a flag signal as a first designated flag value when the startcode emulation prevention pattern is detected. The method further includes the step of detecting whether the input bit-stream includes a startcode, and directly outputting the input bit-stream and setting the flag signal as a second designated flag value when the startcode is detected.
    Type: Application
    Filed: February 25, 2009
    Publication date: September 10, 2009
    Inventors: Yi-Chen Tseng, Cheng-Ying Yu, Chao-An Hsieh
  • Patent number: 7557740
    Abstract: A decoding method is adapted to be implemented using a Context-based Adaptive Binary Arithmetic Coding (CABAC) decoding apparatus, and includes: initializing a plurality of context variables; storing the context variables; performing arithmetic decoding of a syntax element according to the context variables so as to output a decoded syntax element and an update signal; and updating at least one of the context variables according to the update signal. At least one of the context variables is pre-initialized in the initializing step before a bit stream ready.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: July 7, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chao-An Hsieh, Chi-Wang Chai, Kai Wen Chuang
  • Patent number: 7541273
    Abstract: A method for forming bumps is disclosed. First, a substrate having a surface and an under bump metallurgy layer formed thereon is provided, and a portion of the under bump metallurgy layer is removed thereafter. Next, a mask having a metal layer thereon is disposed over the surface of substrate, in which the mask includes at least one opening for exposing the under bump metallurgy layer. Subsequently, a metal is disposed in the opening and the mask having the metal layer is removed.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: June 2, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chueh-An Hsieh, Li-Cheng Tai
  • Publication number: 20090132756
    Abstract: A portable flash memory storage device that may show its remaining lifetime according to this invention is provided, in which an average erase count that is stored may be read and, after being processed and converted, is formed into a piece of information on its remaining lifetime that is further shown on a display screen of a display module in the portable flash memory storage device, and an erase is implemented on the portable flash memory storage device for an automatic update of average erase count, allowing a user to decide to replace the device or not depending on a latest remaining lifetime information.
    Type: Application
    Filed: January 18, 2008
    Publication date: May 21, 2009
    Inventor: Hsiang-An Hsieh
  • Patent number: 7518241
    Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu