Abstract: A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks.

Abstract: A limited slip differential includes a driving plate, backing plates, differential gear assemblies, and a transmission assembly engaged together inside a sealed casing where fluid is pumped. The driving plate has pairs of communicated openings for interlocking two gears of each gear assembly, which extend by opposite directions from the driving plate for separately engaging with the transmission assembly. While synchronously rotating the plates, the gear assemblies are alternatively soaked into the fluid and each permits the fluid passing among the gears for adjusting the rotational speed. In the event that the rotational speed difference of axle shafts of the vehicle exceeds a threshold value, the LSD applies at least one gear assembly to generate a back pressure and efficiently block the fluid passing through the gears for limiting mutual rotational speed difference, hence achieving a limited-slip effect.

Abstract: A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table.

Abstract: A processing device including a control unit and a power amplifier is disclosed. The control unit generates a plurality of control signals according to an input signal. The power amplifier includes a plurality of switches. The control signals control the switches to turn on or off such that a short through current does not occur in the power amplifier.

Abstract: A processing device including a control unit and a power amplifier is disclosed. The control unit generates a plurality of control signals according to an input signal. The power amplifier includes a plurality of switches. The control signals control the switches to turn on or off such that a short through current does not occur in the power amplifier.

Abstract: The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible.

Abstract: The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible.

Abstract: A method and an apparatus for estimating temperature are provided for estimating a temperature of a test point in a space with an air conditioner. In the method, a first and a second sensor device are deployed in the space, wherein the second sensor device is deployed at the test point. Then, state parameters and temperature transformation functions are defined according to temperatures detected by the first and the second sensor devices and a state of the air conditioner during a predetermined time period. After the second sensor device is removed, a current state of the air conditioner is determined by reference temperatures detected by the first sensor device and the state parameters. One of the temperature transformation functions is selected according to the current state, and a current temperature of the test point is estimated by using the selected temperature transformation function and the reference temperatures.

Abstract: A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency.

Abstract: An antenna sense circuit includes a detector and a level shifter. The detector consists of a voltage drop component, a transistor component, a first resistor component, and a second resistor component. The voltage drop component is coupled between a first power supply and a first terminal of the first resistor component. The second resistor component has a first terminal coupled to a second terminal of the first resistor component and a second terminal coupled to a second power supply. The transistor component has a control terminal coupled to the second terminal of the first resistor component and the first terminal of the second resistor component, a second connection terminal coupled to the first power supply, and a first connection terminal for outputting a first detecting signal. The level shifter adjusts a voltage level of the first detecting signal to generate a second detecting signal.

Abstract: An adaptive pulse width control power conversion device includes a pulse width adjustable pulse frequency module (PFM) control circuit, a pulse width modulation (PWM) control circuit, a PWM/PFM switching unit, a switching circuit, and a load status detection circuit. When the power conversion device is to be switched from a PWM mode to a PFM mode, pulse width of a series of PFM control signals is sequentially adjusted from a low value to a high value according to a predetermined pulse width increment until an optimum pulse width is determined and thereafter, an output voltage is supplied to a load in the PFM mode, whereby ripple of output voltage in the PFM mode can be improved and improved stability of output of the power conversion device is realized.

Abstract: A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block.

Abstract: An electronic memory device includes a controller and a memory unit. The controller includes a micro processor, a host interface, a memory unit interface connected to the memory unit, a data cache area for provisionally storing data, an ECC unit coupled to the memory unit for testing whether there is any error bit in the data or not, and an error correcting unit coupled to the memory unit. If an error bit in the data is found and can be dealt by the ECC unit, the error bit is then directly recovered by the ECC unit. However, if the error bit exceeds beyond the processing capability of the ECC unit, the error correcting unit is selected to primarily invert predetermined data bit till the number of the error can be successfully recovered by the ECC unit.

Abstract: A semiconductor package and a manufacturing method thereof are provided. A carrier having an adhesion layer is provided. A plurality of chips are disposed on the adhesion layer, wherein an active surface of each chip faces the adhesion layer. A molding compound is formed for encapsulating the chips to form a chip-redistribution encapsulant having a first surface and a second surface, wherein the first surface has a chip area and a peripheral area. The carrier and the adhesion layer are removed, so that the chip-redistribution encapsulant exposes the active surface of each chip. A plurality of solder balls are uniformly formed in the chip area and the peripheral area. The second surface of the chip-redistribution encapsulant is grinded to reduce the thickness of the chip-redistribution encapsulant, wherein the solder balls provide the chip-redistribution encapsulant with a uniform support. The chip-redistribution encapsulant is sawn to form a plurality of packages.

Abstract: An electronic storage device (320) for connecting with a host system (100) includes a storage unit (360) including at least one memory segment which has at least one physical block, a memory unit (350) receiving access commands sent from the host system, and a control unit (340) connecting with said memory unit. Each of the access commands contains at least a logical address which corresponds to a physical block. The control unit determines the command execution order of the access commands according to adjacent extent of the physical blocks in said memory segment to which the logical addresses of said access commands correspond. A control method of the electronic storage device is also disclosed in the present invention.

Abstract: A storage control apparatus capable of analyzing volume information and a control method thereof is provided. The present storage device controller comprises a volume information analysis module, volume information memory, a display device interface and a power regulation circuit to display the volume information on the display device through the display device interface so that a user can independently read the storage medium and analyze the volume information, regardless of whether it is connected or disconnected.

Abstract: A solid state semiconductor storage device with temperature control function comprises a non-volatile memory unit, a temperature sensing element, and a control unit. The temperature sensing element is used for sensing the operation temperature of the solid state semiconductor storage device so as to provide a temperature sensing signal to the control unit. According to the temperature sensing signal, the control unit controls the operation mode of the solid state semiconductor storage device for achieving the function of temperature control.

Abstract: A first dielectric layer is formed on a mold having a surface and protruding components and covers the protruding components. At least one electronic component having an active surface, a back surface, and contacts formed on the active surface is disposed on the first dielectric layer. The active surface is faced to the first dielectric layer, and the contacts are corresponding to the protruding components. A second dielectric layer is formed on the first dielectric layer and a carrier is disposed on the back surface of the electronic component. Openings located corresponding to the contacts are further formed within the first dielectric layer by the protruding components in an imprinting step, such that when the mold is removed, the contacts are exposed from the openings.

Abstract: Storage apparatus can support various memory units with different standards based on the method which drives the power control-and-switch circuit in the power management unit according to a control signal caused by the ID code of a memory unit to control the second booster for further increasing the level of the external voltage or control the second regulator for further regulating or decreasing the level of the external voltage.

Abstract: A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table.