Abstract: A display apparatus is provided. The display apparatus includes a display module and multiple light-emitting driving circuits. Each of the light-emitting driving circuits includes a timing control circuit and a driving circuit. The timing control circuit receives multiple clock signals and a previous light-emitting timing signal to provide a light-emitting timing signal and an internal voltage. The driving circuit receives a first phase signal among multiple phase signals and the internal voltage to provide a light-emitting driving signal to the display module based on the first phase signal and the internal voltage. The phase signals all present disabled levels during a vertical blank period.

Abstract: A method performed by a User Equipment (UE) for a Layer1/Layer2 Triggered Mobility (LTM) operation is provided. The method receives, from a source cell, an LTM cell switch command Medium Access Control (MAC) Control Element (CE) including a Timing Advance Command (TAC) field. The method switches from the source cell to a target cell in response to receiving the LTM cell switch command MAC CE. In a case that the TAC field is set to an invalid value, the method performs a Random Access (RA) procedure with the target cell upon switching to the target cell, where a type of the RA procedure depends on whether the LTM cell switch command MAC CE further includes a Contention-Free Random Access (CFRA)-related field. In a case that the TAC field is set to a valid value, the method skips the RA procedure with the target cell upon switching to the target cell.

Abstract: A method performed by a User Equipment (UE) for Layer 1/Layer 2 Triggered Mobility (LTM) is provided. The method receives, from a source cell, a Cell Switch Command (CSC) Medium Access Control (MAC) Control Element (CE), the CSC MAC CE indicating a target cell, Timing Advance (TA) information, and a Transmission Configuration Indicator (TCI) state. The method determines whether the TA information is valid. In a case that the TA information is valid, the method determines a pathloss based on a pathloss reference signal associated with the TCI state. In a case that the TA information is not valid, the method determines whether the CSC MAC CE includes Contention-Free Random Access (CFRA) information, and then determines the pathloss based on a Synchronized Signal Block (SSB) indicated in the CFRA information in a case that the CSC MAC CE includes the CFRA information.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a fin spacer layer adjacent to the S/D structure. The bottom surface of the fin spacer layer is lower than a bottom surface of the S/D structure.

Abstract: A controller for controlling a blocking switch of a power converter is provided. The controller includes a control pin and a sensing circuit. The control pin is coupled to a control terminal of the blocking switch and an output terminal of the blocking switch. The sensing circuit includes a control switch and a judgment circuit. A first terminal of the control switch is coupled to the control pin. A second terminal of the control switch is coupled to a reference low voltage. The judgment circuit turns on the control switch during a period when the blocking switch is turned off to obtain a sensing current value of a current flowing through the control switch. When the sensing current value is lower than a reference current value, the judgment circuit provides a notification signal for allowing the blocking switch to be turned on.

Abstract: A controller for controlling a blocking switch of a power converter is provided. The controller includes a control pin and a sensing circuit. The control pin is coupled to a control terminal of the blocking switch and an output terminal of the blocking switch. The sensing circuit includes a control switch, a variable resistance circuit, and a judgment circuit. A first terminal of the control switch is coupled to the control pin. The variable resistance circuit is coupled between a second terminal of the control switch and a reference low voltage. The judgment circuit controls the variable resistance circuit to provide a detection resistance value with a minimum value, and turns on the control switch to obtain a sensing voltage value. When the detection resistance value has a maximum value and the sensing voltage value is lower than a reference voltage value, the judgment circuit provides a notification signal.

Abstract: A driving circuit includes a driving transistor, first to second capacitors and first to third switching transistors. The driving transistor is configured to control a driving current provided to a light emitting element to emit light. The first capacitor includes a first terminal coupled to a gate terminal of the driving transistor. The first switching transistor coupled between a second terminal of the first capacitor and a driving voltage terminal. The second switching transistor includes a first terminal coupled to a gate terminal of the first switching transistor and a second terminal coupled to a first reference voltage terminal. The third switching transistor coupled between a gate terminal of the second switching transistor and a second reference voltage terminal. The second capacitor includes a first terminal coupled to a gate terminal of the third switching transistor and a second configured to receive a sweep signal.

Abstract: The present invention relates to a method of image fusion, which uses the brightness difference of the current frame and the previous frame to determine whether the pixel in a frame image is static or dynamic. If the current pixel is static, the previous corresponding pixel is superimposed onto the current pixel; if the current pixel is dynamic, the previous corresponding pixel is replaced with the current pixel.

Abstract: An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.

Abstract: A heat exchange device and a cooling system are provided. The heat exchange device includes a low-pressure chamber and a high-pressure chamber disposed in the low-pressure chamber. The low-pressure chamber has a first wall for enabling heat exchange and an output portion in communication with the outside to output the low-pressure fluid. The high-pressure chamber has an input portion in communication with the outside to admit the high-pressure fluid and nozzles in communication with the low-pressure chamber. The fluid discharged from the nozzles undergoes a pressure drop and undergoes heat exchange through the first wall. Cooling capability is developed in the heat exchange device and works in the heat exchange device to thereby dispense with a pipeline which must be otherwise provided to link an expansion process and an evaporation process of the fluid and may otherwise cause cooling capability loss, so as to greatly enhance heat exchange capability and cooling efficiency.

Abstract: Pesticidal compositions for improving physical characteristics of pesticide formulations which comprise natural pesticidal oil active ingredients are disclosed. One such composition comprises a pesticidal natural oil active ingredient, a surfactant to disperse the active ingredient in a water emulsion and a polymeric pour point depressant effective to reduce a pour point temperature of the pesticidal natural oil active ingredient. Methods for providing pesticidal compositions and application to control one or more pests are also disclosed.

Abstract: A filter mesh frame is provided. The filter mesh frame includes a first mesh and a second mesh. The first mesh surrounds to form a cylinder with respect to a first pivot direction. The second mesh surrounds the first mesh with respect to a first pivot direction and includes a plurality of bar structures, where the bar structures protrude outward with respect to the first mesh and are disposed parallel to the first pivot direction. A groove parallel to the first pivot direction is formed on one side of each bar structure with respect to the first mesh.

Abstract: A method for configuring a subsequent conditional primary secondary cell addition/change (S-CPAC) to a UE is provided. The method receives from a source cell an S-CPAC configuration that includes an RRC configuration for a primary secondary cell (PSCell) and a set of conditions for switching to the PSCell. The method receives a secondary key (SK)-counter list associated with the S-CPAC. The list includes one or more SK-counter entries arranged in an order. The method stores the S-CPAC configuration and the SK-counter list. After determining that one or more of the set of conditions are satisfied, the method selects a first SK-counter entry of the SK-counter list and configures the UE with the S-CPAC configuration to switch from another PSCell to the PSCell. In configuring the UE with the S-CPAC configuration, the first SK-counter entry is applied. The method then removes the first SK-counter entry from the SK-counter list.

Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.

Abstract: A user equipment (UE) and a method for beam indication in a multi-transmission and reception point (MTRP) are provided. The method includes: receiving, from a base station (BS), first downlink control information (DCI) including a first transmission configuration indication (TCI) field indicating a first TCI state, the first DCI being associated with a first value; receiving, from the BS, second DCI including a second TCI field indicating a second TCI state, the second DCI being associated with a second value; performing, based on the first TCI state, a first uplink (UL) transmission; and performing, based on the second TCI state, a second UL transmission. The first UL transmission is scheduled by third DCI associated with the first value, and the second UL transmission is scheduled by fourth DCI associated with the second value.

Abstract: A photoelectric sensing device including a substrate, a first pixel structure, a second pixel structure and a first bus line. The first pixel structure is disposed on the substrate and includes a first photoelectric sensing component, wherein the first photoelectric sensing component has a first semiconductor layer. The second pixel structure is disposed on the substrate and includes a second photoelectric sensing component, wherein the second photoelectric sensing component has a second semiconductor layer. The first bus line is disposed on the substrate and located between the first semiconductor layer and the second semiconductor layer, wherein the first bus line is electrically connected to the first pixel structure and the second pixel structure.

Abstract: A membrane keyboard and manufacturing method thereof, the manufacturing method comprises the following steps: forming a first positioning hole on an upper circuited layer, forming a second positioning hole and a plurality of hollow portions on a spacer layer, forming a third positioning hole on a lower circuited layer, wherein a minimum diameter of the second positioning hole is smaller than a minimum diameter of the first positioning hole and a minimum diameter of the third positioning hole; adhering the upper circuited layer, the spacer layer and the lower circuited layer, to form a restoring member positioning hole; placing the membrane circuit board in the restoring member assembly fixture and passing the restoring member positioning hole through a locating pillar of the restoring member assembly fixture, with an inner wall of the second positioning hole abutting the locating pillar.

Abstract: A method performed by an 8-TX UE for full power transmissions is provided. The method transmits an IE for reporting capability information. The method receives a PUSCH configuration for configuring the 8-TX UE with a CB PUSCH transmission, a full power mode 1, and one of a partial coherent codebook subset with two antenna groups, a partial coherent codebook subset with four antenna groups, and a non-coherent codebook subset. The method receives DCI including an SRI and an additional TPMI for indicating an 8-port SRS resource. The method then performs the CB PUSCH transmission using the full power mode 1. The IE includes a field indicating support for the full power mode 1 and a field indicating support for one of the partial coherent codebook subset with two antenna groups, the partial coherent codebook subset with four antenna groups, and the non-coherent codebook subset.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.