Abstract: A detection device, including a substrate, a switch element, a photosensitive element, and a planarization layer, is provided. The switch element is disposed on the substrate. The photosensitive element includes a bottom electrode, a top electrode, and a first semiconductor disposed between the bottom electrode and the top electrode. The planarization layer is disposed between the bottom electrode and the switch element. The bottom electrode is coupled to the switch element.

Abstract: An embodiment of the invention provides an electrocardiography (ECG) signal processing device. The ECG signal processing device includes a first part, a second part and a flexible printed circuit board. The first part may comprise a first electrode and a processing circuit. The second part includes a second electrode. The flexible printed circuit board is coupled to the first part and the second part to fold the first part and the second part. When a closed loop is formed between the first electrode and the second electrode, the processing circuit obtains an ECG signal from the user.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.

Abstract: A method for generating a three-dimensional (3D) global pose includes: receiving an image and performing a detection operation to detect a human body in the image; obtaining a two-dimensional (2D) heatmap that is related to a skeleton structure of the human body and that includes a plurality of human keypoints, and obtaining a plurality of 2D coordinate sets each indicating a position of a corresponding one of the human keypoints; performing a 3D human pose estimation operation on the plurality of 2D coordinate sets to obtain a 3D human pose that is related to the skeleton structure in a local coordinate system, and that includes a plurality of 3D keypoints corresponding to the plurality of human keypoints, respectively; and based on the 3D human pose, using a numerical optimization solver to generate a 3D global pose in a world coordinate system.

Abstract: A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed. In one example, a disclosed RF screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. The conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. Each of the individual openings has a triangular shape.

Abstract: A topical subcutaneous microcirculation detection device includes a first light source module, a second light source module, a lens plate, a first light sensor, and a second light sensor. The first and second light source modules are configured to emit first and second illumination beams, respectively. A flat plate portion of the lens plate is disposed to lean against a first portion of skin of a subject. A convex surface of a first convex lens portion of the lens plate is disposed to push into a second portion of the skin of the subject. The first and second illumination beams are reflected into first and second reflected beams by the first and second portions of the skin, respectively. The first and second reflected beams are transmitted to the first and second light sensors, respectively.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

Abstract: The present invention provides an optical imaging lens. The optical imaging lens comprises five lens elements positioned in an order from an object side to an image side. Through controlling the convex or concave shape of the surfaces of the lens elements and satisfying an inequality, the optical imaging lens may be provided with smaller volume and great field of view.

Abstract: A manufacturing method of an electronic device is provided. The manufacturing method of the electronic device includes following steps: providing a substrate; bonding at least one electronic component to the substrate, wherein the at least one electronic component is mainly driven by a reverse bias in an operating mode; applying a forward bias to the at least one electronic component, and determining whether the at least one electronic component is normal or failed; and transporting the substrate configured with the at least one electronic component determined to be normal to a next production site or repairing the at least one electronic component determined to be failed.

Abstract: A photomask cleaning tool includes various components to automatically remove a particle from a pellicle, such as a multi-jet nozzle to standardize and control the use of a gas to remove the particle, an ultrasonic probe to loosen the particle from the surface of the pellicle, a plurality of multi-jet nozzles to direct gas toward the particle from different directions, a control system to control the automated blower for various sizes and shapes of photomasks and for optimized particle removal techniques, and/or the like. In this way, the photomask cleaning tool is capable of removing a particle from a pellicle of a photomask in a manner that increases the effectiveness of removing the particle and reduces the likelihood of damage to the pellicle, which would otherwise result in expensive and time-consuming photomask rework.

Abstract: Disclosed is a light-emitting diode which includes a light-emitting epitaxial layered unit, an insulation layer, a transparent conductive layer, a protective layer, a first electrode, and a second electrode. The light-emitting epitaxial layered unit includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer sandwiched between the first and second semiconductor layers, and has a first electrode region which includes a pad area and an extension area. The insulation layer is disposed on the first semiconductor layer and at the extension area of the first electrode region. Also disclosed is a method for manufacturing the light-emitting diode.

Abstract: A package structure is provided. The package structure includes a substrate and a chip-containing structure bonded to the substrate. The package structure also includes a warpage-control element attached to the substrate. The warpage-control element has a protruding portion extending into the substrate.

Abstract: A layout method, a non-transitory computer-readable medium, and an associated integrated circuit are provided. The non-transitory computer-readable medium records a software program for performing the layout method of the integrated circuit having Q circuit blocks. The layout method includes the following steps. K gate-controlled elements and (K?1) buffers are placed on the edge of a qth circuit block. The K gate-controlled elements are connected between a supply voltage terminal and the qth circuit block. (K?1) gate-controlled elements, including an SEL[1]-th gate-controlled element, are selected as (K?1) source nodes. Another (K?1) gate-controlled elements, other than the SEL[1]-th gate-controlled element, are selected as (K?1) destination nodes. The (K?1) buffers are routed as (K?1) delayed gating lines connected between the (K?1) source nodes and the (K?1) destination nodes.

Abstract: A method for fabricating a semiconductor structure, including disposing a mask at a first position in a first chamber, generating a first plurality of ions toward the mask by an ionizer, forming a photoresist layer on a substrate, receiving the substrate in the first chamber, and exposing the photoresist layer with actinic radiation through the mask in the first chamber.

Abstract: A semiconductor device includes a substrate, a buffer layer, a gradient layer, an active layer, a window layer, and an optical filtering layer. The substrate includes a first element and a second element. The buffer layer is disposed on the substrate. The gradient layer is formed on the buffer layer, and includes sublayers. Each sublayer includes the first, second, and third elements. For each sublayer, a lattice constant thereof is adjusted by changing a ratio of the second element to the third element. The active layer is formed on the gradient layer, and includes the first, second, and third elements. The window layer is formed on the active layer. The optical filtering layer includes the first, second, and third elements, and is formed on the window layer to block a portion of light having a wavelength in a predetermined wavelength range.

Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.

Abstract: A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.