Patents by Inventor An-Hung Lin
An-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971624Abstract: High-voltage transistor devices with two-step field plate structures and methods of fabricating the transistor devices are provided. An example high voltage transistor device includes: a gate electrode disposed over a substrate between a source region and a drain region, a first film laterally extending from over the gate electrode to over a drift region laterally arranged between the gate electrode and the drain region, a second film laterally extending over a portion of the drift region adjacent to the drain region and away from the gate electrode, and a field plate laterally extending from over the first film to over the second film. A first thickness vertically from a top surface of the gate electrode to a bottom surface of the field plate is smaller than a second thickness vertically from a top surface of the portion of the drift region to the bottom surface of the field plate.Type: GrantFiled: March 19, 2018Date of Patent: April 6, 2021Assignee: Macronix International Co., Ltd.Inventors: Han-Lun Wang, An-Hung Lin, Wei-Chih Lin, Xin-You Chen, Bo-Jui Huang
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Publication number: 20190288112Abstract: High-voltage transistor devices with two-step field plate structures and methods of fabricating the transistor devices are provided. An example high voltage transistor device includes: a gate electrode disposed over a substrate between a source region and a drain region, a first film laterally extending from over the gate electrode to over a drift region laterally arranged between the gate electrode and the drain region, a second film laterally extending over a portion of the drift region adjacent to the drain region and away from the gate electrode, and a field plate laterally extending from over the first film to over the second film. A first thickness vertically from a top surface of the gate electrode to a bottom surface of the field plate is smaller than a second thickness vertically from a top surface of the portion of the drift region to the bottom surface of the field plate.Type: ApplicationFiled: March 19, 2018Publication date: September 19, 2019Applicant: Macronix International Co., Ltd.Inventors: Han-Lun Wang, An-Hung Lin, Wei-Chih Lin, Xin-You Chen, Bo-Jui Huang
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Patent number: 9245996Abstract: A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.Type: GrantFiled: January 2, 2014Date of Patent: January 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Bo-Jui Huang, Kun-Yi Chou, Hsiao-Wen Liu, Kai-Cheng Chang
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Publication number: 20150187933Abstract: A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Bo-Jui Huang, Kun-Yi Chou, Hsiao-Wen Liu, Kai-Cheng Chang
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Publication number: 20150180311Abstract: A motor controller and a cooling method thereof are provided. The motor controller includes: a first power module; a second power module; a first heat sink having first fins; a second heat sink having second fins; a first partition board; a second partition board; a housing disposed at external sides of the first and second partition boards, with a first channel formed between the housing and the first partition board; a conduit connected to a rear end of the first heat sink and extending to an outlet of the housing; a first flow channel; and a second flow channel passing through the first channel and the gaps of the second fins, for second cold air to be introduced, and processed by a heat exchange process performed by the second power module to generate second hot air that is expelled to the outlet of the housing through the second flow channel.Type: ApplicationFiled: October 20, 2014Publication date: June 25, 2015Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kou-Tzeng LIN, Li-Fen LIU, Min-Chuan WU, An-Hung LIN, Shin-Hung CHANG, Po-Hua CHANG
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Patent number: 8829850Abstract: An interactive charging management system and a method thereof are provided. The present method includes following steps. A leakage event is detected when an electric vehicle is connected with a charging post. When the leakage event is not detected, the charging post is controlled to enter a charging state from a ready state, so as to continuously supply a charging power to the electric vehicle until the electric vehicle is completely charged. When the leakage event is detected, the charging post is controlled to stop supplying the charging power to the electric vehicle, and the electric vehicle is indicated to go offline, so as to perform a leakage test and determine whether to resume the ready state. When the charging post cannot resume the ready state, a service notice is issued to notify a curing unit to process.Type: GrantFiled: February 17, 2011Date of Patent: September 9, 2014Assignee: Industrial Technology Research InstituteInventors: Wen-Shu Chiang, Chin-Pin Chien, An-Hung Lin
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Patent number: 8803235Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: GrantFiled: October 3, 2013Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Patent number: 8786362Abstract: A Schottky diode having a current leakage protection structure includes a Schottky diode unit, a first isolation portion and a second isolation portion. The Schottky diode unit is defined in a substrate and includes a metalized anode, an active region having dopants of first conductive type, a cathode and at least one isolation structure. The first isolation portion having dopants of second conductive type is formed between substrate and active region, and the first isolation portion includes a first well disposed beneath active region, and a first guard ring surrounding active region and connecting to the first well. The second isolation portion having dopants of first conductive type is formed between substrate and the first isolation portion, and the second isolation portion includes a second well disposed beneath the first well, and a second guard ring surrounding the first guard ring and connecting to the second well.Type: GrantFiled: June 4, 2013Date of Patent: July 22, 2014Assignee: United Microelectronics CorporationInventors: An-Hung Lin, Wei-Shan Liao, Bo-Jui Huang, Hong-Ze Lin, Ting-Zhou Yan, Wen-Chun Chang
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Publication number: 20140048877Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.Type: ApplicationFiled: August 14, 2012Publication date: February 20, 2014Inventors: Wei-Shan LIAO, An-Hung LIN, Hong-Ze LIN, Bo-Jui HUANG
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Publication number: 20140035034Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: ApplicationFiled: October 3, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Patent number: 8643104Abstract: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.Type: GrantFiled: August 14, 2012Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventors: Wei-Shan Liao, An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang
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Patent number: 8587058Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.Type: GrantFiled: January 2, 2012Date of Patent: November 19, 2013Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
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Patent number: 8581338Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: GrantFiled: May 12, 2011Date of Patent: November 12, 2013Assignee: United Microelectronics Corp.Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Patent number: 8508187Abstract: An interactive charging management system and a method thereof are provided. The method is applicable to a plurality of electric vehicles, and which includes dynamically adjusting usable power information respectively provided by a plurality of charging posts respectively corresponding to and coupled to the electric vehicles according to demand power information of the respective electric vehicles; and making the charging posts non-uniformly provide a plurality of charging powers to the respective electric vehicles according to the adjusted usable power information.Type: GrantFiled: February 16, 2011Date of Patent: August 13, 2013Assignee: Industrial Technology Research InstituteInventors: Wen-Shu Chiang, Chin-Pin Chien, An-Hung Lin
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Patent number: 8482063Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.Type: GrantFiled: November 18, 2011Date of Patent: July 9, 2013Assignee: United Microelectronics CorporationInventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
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Publication number: 20130168767Abstract: The present invention provides a lateral diffused metal-oxide-semiconductor device including a first doped region, a second doped region, a third doped region, a gate structure, and a contact metal. The first doped region and the third doped region have a first conductive type, and the second doped region has a second conductive type. The second doped region, which has a racetrack-shaped layout, is disposed in the first doped region, and has a long axis. The third doped region is disposed in the second doped region. The gate structure is disposed on the first doped region and the second doped region at a side of the third doped region. The contact metal is disposed on the first doped region at a side of the second doped region extending out along the long axis, and is in contact with the first doped region.Type: ApplicationFiled: January 2, 2012Publication date: July 4, 2013Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen, Ming-Yong Jian
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Patent number: 8466019Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.Type: GrantFiled: October 6, 2011Date of Patent: June 18, 2013Assignee: Vanguard International Semiconductor CorporationInventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
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Publication number: 20130126968Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: An-Hung LIN, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Wei-Chun Chang, Chun-Yao Lee, Kun-Yi Chou
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Publication number: 20120286359Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
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Patent number: D1024932Type: GrantFiled: March 10, 2022Date of Patent: April 30, 2024Assignee: WALSIN LIHWA CORPORATIONInventors: Ko-Ming Chen, Shih-Hsiang Wang, An-Hung Lin, Min-Chuan Wu, Shao-Pei Lin, Chien-Chung Ni, Chun-Ying Lin