Patents by Inventor An-Kai Chang

An-Kai Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230086525
    Abstract: The relay safety system provided by the present invention includes a relay, an emergency stop device, a trigger detection circuit, a sticking detection circuit, and a power-off circuit. The emergency stop device is used to generate an emergency stop signal. The trigger detection circuit connects the relay and the emergency stop device, and is used to convert the emergency stop signal into a trigger signal. The sticking detection circuit is connected to the trigger detection circuit and the relay, and is used to detect the sticking signal generated by the relay, and generate a power-off signal according to the trigger signal and the sticking signal. The power-off circuit is connected to the emergency stop device, the relay and the sticking detection circuit, and receives the power-off signal, and disconnects the power of the relay according to the power-off signal.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Shun-Kai CHANG, Yi-Hung CHEN, Yen-Shun HUANG
  • Publication number: 20230085153
    Abstract: The present invention provides a controller of a tethering device, wherein the controller includes a tethering manager and a cellular configuration manager. The tethering manager is configured to generating tethering parameters of at least one network interface of the tethering device, wherein the at least one network interface of the tethering device is used to communicate with an electronic device, and the electronic device shares a cellular network of the tethering device via the at least one network interface. The cellular configuration manager is configured to determine a first cellular mode according to the tethering parameters of at least one network interface, to control a cellular modem to use the first cellular mode.
    Type: Application
    Filed: September 5, 2022
    Publication date: March 16, 2023
    Applicant: MEDIATEK INC.
    Inventors: Sheng-Kai Chang, Wang-Hsin Kuo
  • Publication number: 20230081804
    Abstract: A display device defines a display area and a non-display area and includes a thin film transistor array substrate, a circuit board, and a light modulating layer. The thin film transistor array substrate includes a glass substrate, a driving circuit, and at least one conductive part. The opposing first and second surfaces of the glass substrate define at least one through hole penetrating both, the through hole accommodating one conductive part which extends to electrically connect the driving circuits on the first and second surfaces. The circuit board is electrically connected to the driving circuit on the first surface. The light modulating layer is in the display area and is on the second surface. The light modulating layer is electrically connected to the driving circuit on the second surface.
    Type: Application
    Filed: February 23, 2022
    Publication date: March 16, 2023
    Inventors: DENG-KAI CHANG, CHING-TUNG WANG, YI-HUNG TSAI, CHIEN-CHANG WANG, AN-CHOU CHEN
  • Publication number: 20230071738
    Abstract: Disclosed are a manual and remote control forward and reverse rotation control device and its control method for DC brushless ceiling fans. The control device includes a power supply, a remote control, a manual control switch assembly and a ceiling fan brushless motor which are electrically connected with one another. A gear position signal can be inputted from a remote end to determine and control the forward and reverse rotations of a brushless motor of the ceiling fan. The remote control can be connected externally by an existing control line or a manual controller module without requiring additional wiring, so as to improve the diversity of structural mechanism, increase the versatility of remote operation, and achieve good functionality and variability of applications.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 9, 2023
    Inventor: Yi-Kai CHANG
  • Publication number: 20230061022
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai CHANG, Chia-Hung CHU, Shuen-Shin LIANG, Keng-Chu LIN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20230068965
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hung CHU, Shuen-Shin LIANG, Hsu-Kai CHANG, Tzu Pei CHEN, Kan-Ju LIN, Chien CHANG, Hung-Yi HUANG, Sung-Li WANG
  • Publication number: 20230064722
    Abstract: The present invention provides a control method of a tethering device, wherein the control method includes the steps of: receiving cellular information of the tethering device, and determining a first tethering mode according to the cellular information; and using the first tethering mode to configure at least one interface of the tethering device, wherein the at least one interface of the tethering device is used to communicate with an electronic device, and the electronic device shares a cellular network of the tethering device via the at least one interface.
    Type: Application
    Filed: July 20, 2022
    Publication date: March 2, 2023
    Applicant: MEDIATEK INC.
    Inventors: Sheng-Kai Chang, Wang-Hsin Kuo
  • Patent number: 11594609
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 11581259
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 11579531
    Abstract: The present disclosure is directed to organotin cluster compounds having formula (I) and their use as photoresists in extreme ultraviolet lithography processes.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai Chang, Chi-Ming Yang, Jui-Hsiung Liu, Jui-Hung Fu, Hsin-Yi Wu
  • Patent number: 11573495
    Abstract: A control system includes a plurality of pressure sensors, each to detect a pressure in a respective dynamic gas lock (DGL) nozzle control region of a plurality of DGL nozzle control regions. Each DGL nozzle control region includes one or more DGL nozzles. The control system includes a plurality of mass flow controllers (MFCs). Each MFC of the plurality of MFCs is to control a flow velocity in a respective DGL nozzle control region of the plurality of DGL nozzle control regions. The control system includes a controller to selectively cause one or more MFCs of the plurality of MFCs to adjust flow velocities in one or more DGL nozzle control regions of the plurality of DGL nozzle control regions based on pressures detected by the plurality of pressure sensors in DGL nozzle control regions of the plurality of DGL nozzle control regions.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Kai Chang, Yu Sheng Chiang, Yu De Liou, Chi Yang, Ching-Juinn Huang, Po-Chung Cheng
  • Publication number: 20230029867
    Abstract: A blocking material is selectively deposited on a bottom surface of a back end of line (BEOL) conductive structure such that a barrier layer is selectively deposited on sidewalls of the BEOL conductive structure but not the bottom surface. The blocking material is etched such that copper from a conductive structure underneath is exposed, and a ruthenium layer is deposited on the barrier layer but less ruthenium is deposited on the exposed copper. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is substantially absent from the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium layer reduces surface roughness within the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance.
    Type: Application
    Filed: February 25, 2022
    Publication date: February 2, 2023
    Inventors: Shu-Cheng CHIN, Ming-Yuan GAO, Chun-Kai CHANG, Chen-Yi NIU, Hsin-Ying PENG, Chi-Feng LIN, Hung-Wen SU
  • Publication number: 20230025324
    Abstract: The present disclosure discloses a dual-processor electronic apparatus operation method used in a dual-processor electronic apparatus that includes steps outlined below. A first processor is activated in an initialization procedure. A second processor is activated by the first processor to enter an operation mode. The first processor is deactivated in the operation mode, and the second processor executes a predetermined procedure. Whether a predetermined event occurs during the execution of the predetermined procedure is determined by the second processor such that event information is stored when the predetermined event occurs and the first processor is activated. The event information is accessed and processed by the first processor.
    Type: Application
    Filed: December 28, 2021
    Publication date: January 26, 2023
    Inventors: Fu-cheng Chen, Chao-kai Chang, Yao-chang Hsieh
  • Patent number: 11563083
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Shuen-Shin Liang, Sung-Li Wang, Hsu-Kai Chang, Chia-Hung Chu, Chien-Shun Liao, Yi-Ying Liu
  • Publication number: 20230016100
    Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.,LTD.
    Inventors: Hsu-Kai CHANG, Keng-Chu LIN, Sung-Li WANG, Shuen-Shin LIANG, Chia-Hung CHU
  • Publication number: 20230016515
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20230009077
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The method includes forming first and second fin structures on a substrate, forming n- and p-type source/drain (S/D) regions on the first and second fin structures, respectively, forming first and second contact openings on the n- and p-type S/D regions, respectively, forming a carbon-based layer in the first and second contact openings, performing a remote plasma treatment with radicals on the carbon-based layer to form a remote plasma treated layer, selectively removing a portion of the remote plasma treated layer, forming a p-type work function metal (pWFM) silicide layer on the p-type S/D region, and forming an n-type work function metal (nWFM) silicide layer on the pWFM silicide layer and on the n-type S/D region.
    Type: Application
    Filed: February 25, 2022
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Huan-Chieh SU, Lo-Heng CHANG, Shih-Chuan CHIU, Hsu-Kai CHANG, Ko-Feng CHEN, Keng-Chu LIN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20230009981
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 12, 2023
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Hsu-Kai CHANG, Sung-Li WANG, Kuan-Kan HU, Shuen-Shin LIANG, Kao-Feng LIN, Hung Pin LU, Yi-Ying LIU, Chuan-Hui SHEN
  • Publication number: 20230012147
    Abstract: The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hung CHU, Ding-Kang SHIH, Keng-Chu LIN, Pang-Yen TSAI, Sung-Li WANG, Shuen-Shin LIANG, Tsungyu HUNG, Hsu-Kai CHANG
  • Patent number: 11541687
    Abstract: A reinforced prepreg which is applied to a wear-resistant layer structure of a braking track is provided. The reinforced prepreg includes a fiber fabric and a mixture mixed with the fiber fabric. The mixture includes a resin and a plurality of needle-shaped crystals having microscale or nanoscale sizes mixed with the resin.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 3, 2023
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventors: Chih-Kai Chang, Yao-Tun Chiang, Ching-Yao Lin