Patents by Inventor An-Li LI

An-Li LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240405070
    Abstract: In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: December 5, 2024
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20240406709
    Abstract: An apparatus or method for storing records for a plurality of embedded subscriber identity module (eSIM) profiles, wherein a record for each eSIM profile comprises a state of the eSIM profile, receiving, from a first user equipment (UE), a message indicating a first eSIM profile has been deleted from the first UE, changing the state of the first eSIM profile from installed to available, receiving a message requesting the first eSIM profile be allocated to a second UE, changing the state of the first eSIM profile to a state allowing the eSIM profile to be downloaded to the second UE and downloading the first eSIM profile to the second UE.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 5, 2024
    Inventors: Raj S. CHAUGULE, Li LI, Rohan C. MALTHANKAR, Sherman X. JIN, Suraj GUPTA
  • Patent number: 12160787
    Abstract: Disclosed are methods, systems, apparatus, and computer programs for self-learning geofences is disclosed. In one aspect, a method involves gathering a plurality of data points associated with one or more Citizens Broadband Radio Service (CBRS) deployers; determining respective identifiers of the one or more CBRS deployers associated with the plurality of data points; clustering, based on the respective identifiers of the one or more CBRS deployers, the plurality of data points into one or more clusters, where each cluster is associated with one of the one or more CBRS deployers, and where each cluster is associated with a geofence of a network of the one or more CBRS deployers; identifying an opportunity for uploading the one or more clusters to a central server; and uploading the one or more clusters to the central server during the identified opportunity.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: December 3, 2024
    Assignee: Apple Inc.
    Inventors: Li Li, Raj Sukumar Chaugule, En Yang Zhang
  • Patent number: 12160927
    Abstract: This Application sets forth techniques for provisioning and activating an electronic subscriber identity module (eSIM) as a primary SIM for a mobile wireless device that includes a limited functionality physical SIM (pSIM) associated with a particular mobile network operator (MNO) and installed in the mobile wireless device at a time of manufacture. An eSIM associated with the particular MNO is reserved during a sales order process and later activated during device activation after receipt by a user using a secure over-the-air (OTA) cellular connection enabled by the limited functionality pSIM, when a non-cellular connection or other Internet accessible connection is available. Dual SIM device configuration processes can be suppressed during activation of the eSIM. After successful attachment of the mobile wireless device to a cellular wireless network of the particular MNO using credentials of the eSIM, the limited functionality pSIM is disabled.
    Type: Grant
    Filed: August 30, 2023
    Date of Patent: December 3, 2024
    Assignee: Apple Inc.
    Inventors: Raj S. Chaugule, He Zheng, Li Li, Vikram Bhaskara Yerrabommanahalli, Chandiramohan Vasudevan
  • Publication number: 20240394587
    Abstract: A computer-implemented system and method generate a model of a plurality of features of network flow data. The model includes a composition of a plurality of Gaussian components, each of which may be skewed. The features are represented as a multivariate feature vector. Training is performed on the feature data using Gaussian Mixture Model (GMM) using Expectation Maximization. The feature data are assigned to clusters with corresponding probabilities. Once the model has been generated, it may be used to detect outlier activity.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 28, 2024
    Inventors: Anindya ROY, Eugen PANAITESCU, Li LI, Ramesh NATARAJAN
  • Publication number: 20240394292
    Abstract: One or more systems, devices, computer program products and/or computer-implemented methods provided herein facilitate generation of an essentialized document that aids a technician in solving a problem with an asset. In an embodiment, the essentialized document is customizable based on technician skill. In another embodiment, the essentialized document is customizable based on the asset and asset components at issue.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Inventors: Li Li Guan, Zhe Yan, Rong Zhao, Li Bo Zhang, Hao Xiang Wu
  • Publication number: 20240395810
    Abstract: An embodiment includes a device including a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first carbon-containing buffer layer on the first fin. The device also includes and a first epitaxial structure on the first carbon-containing buffer layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Patent number: 12154974
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Chang, Ming-Hua Yu, Li-Li Su
  • Patent number: 12150670
    Abstract: Disclosed is a pet intraurethral incision knife, including a knife rod, a blade, and a guide wire, a blade slot is formed on one side of the knife rod, the hollow cavity is formed inside the knife rod in the length direction, the hollow cavity is communicated with the bottom of the blade slot, the blade can be rotationally retracted inside the blade slot, one end of the guide wire is abutted against an edge of one end of the blade, and the other end thereof passes through the hollow cavity and forms an operating end at one end of the knife rod, such that the operating end drives one end of the guide wire to push the blade to rotate and to be exposed from the opening of the blade slot, the blade can be hidden and stored inside the blade slot before being inserted into a pet urethra.
    Type: Grant
    Filed: July 9, 2024
    Date of Patent: November 26, 2024
    Inventor: Li Li
  • Publication number: 20240388076
    Abstract: The present disclosure discloses an automatic winding module and a highly interchangeable charging module. In the automatic winding module, a winding assembly is disposed in the winding housing so that an output line may be wound in the winding housing. In this manner, any length can be extracted within the range of the total length of the output line when in use. A first connection assembly is configured to be detachably adsorptively connected to a power supply base output member. The power supply base output member has a second connection assembly. As long as a power supply base output member is provided with the second connection assembly, the power supply base output member may be connected to the automatic winding module having a first connection assembly. In this manner, the interchangeability between the automatic winding module and different categories of power supply base output members is implemented.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 21, 2024
    Applicant: ASAP TECHNOLOGY (JIANGXI) CO., LIMITED
    Inventors: Li LI, Xiongwu LI, Jianjun TIAN
  • Publication number: 20240387742
    Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20240387629
    Abstract: A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Wei-Min Liu, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20240387702
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chih-Chiang Chang, Ming-Hua Yu, Li-Li Su
  • Publication number: 20240378291
    Abstract: Under one aspect, a method is provided for protecting a device from a malicious file. The method can be implemented by one or more data processors forming part of at least one computing device and can include extracting from the file, by at least one data processor, sequential data comprising discrete tokens. The method also can include generating, by at least one data processor, n-grams of the discrete tokens. The method also can include generating, by at least one data processor, a vector of weights based on respective frequencies of the n-grams. The method also can include determining, by at least one data processor and based on a statistical analysis of the vector of weights, that the file is likely to be malicious. The method also can include initiating, by at least one data processor and responsive to determining that the file is likely to be malicious, a corrective action.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Li Li, Xuan Zhao, Sepehr Akhavan-Masouleh, John Hendershott Brock, Yaroslav Oliinyk, Matthew Wolff
  • Publication number: 20240379781
    Abstract: A semiconductor device, includes a device layer comprising: a channel region; a gate stack over and along sidewalls of the channel region and a first insulating fin; and an epitaxial source/drain region adjacent the channel region, wherein the epitaxial source/drain region extends through the first insulating fin. The semiconductor device further includes a front-side interconnect structure on a first side of the device layer; and a backside interconnect structure on a second side of the device layer opposite the first side of the device layer. The backside interconnect structure comprises a backside source/drain contact that is electrically connected to the epitaxial source/drain region.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Wei Hao Lu, Li-Li Su, Chien-I Kuo, Yee-Chia Yeo, Wei-Yang Lee, Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240379454
    Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Hui-Lin Huang, Li-Li Su, Yee-Chia Yeo, Chii-Horng Li
  • Patent number: 12142707
    Abstract: A micro light emitting diode panel is provided. The micro light emitting diode panel includes a circuit substrate, a plurality of transistor devices and a plurality of micro light emitting diode devices. The transistor devices are bonded to the circuit substrate. Each of the transistor devices has a semiconductor pattern, a source electrode, a drain electrode and a gate electrode. The source electrode and the drain electrode are electrically connected to the semiconductor pattern. The source electrode, the drain electrode, and the gate electrode are located between the semiconductor pattern and the circuit substrate. The electron mobility of the semiconductor pattern is greater than 20 cm2/V·s. The micro light emitting diode devices are bonded to the circuit substrate, and are electrically connected to the transistor devices respectively.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: November 12, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Ying-Tsang Liu, Chih-Ling Wu
  • Patent number: 12142200
    Abstract: A multi-layer display module includes a first display panel, a second display panel, a driving device, and an image composition control unit. The second display panel is located beside the first display panel and overlaps the first display panel. The first display panel and the second display panel have an interval therebetween. The driving device is configured to simultaneously provide image signals to the first display panel and the second display panel. An object image displayed in the first display panel is a first object image. An object image displayed in the second display panel is a second object image. The image composition control unit is configured to increase a size of the first object image displayed on the first display panel or decrease a size of the second object image displayed on the second display panel according to information of a relative position of an outside viewer.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: November 12, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Yun-Li Li, Kuan-Yung Liao, Sheng-Yuan Sun, Zong Huei Tsai
  • Publication number: 20240373190
    Abstract: Methods, devices, and systems for establishing a geofence for a Non-Public Network (NPN) using an Embedded Subscriber Identity Module (eSIM) associated with the NPN. The method includes receiving, by a receiver of a User Equipment (UE), an eSIM associated with an NPN, where the eSIM includes geofencing data. The UE performs wireless communication using the NPN when the UE is within an area defined by the geofencing data.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 7, 2024
    Inventors: Tao Tao, Divyaprakash P. Bhojkumar, Li Li, Raj S. Chaugule
  • Publication number: 20240371636
    Abstract: A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo