Patents by Inventor An-Li WANG

An-Li WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168085
    Abstract: A substrate with a crack detection function, comprising an installation area for installing hardware, a wiring area, and a detection assembly. The wiring area is set around the installation area. The detection assembly is in the wiring area. The detection assembly includes a plurality of detecting units and a plurality of connecting units. The plurality of detecting units is set around the wiring area. Two ends of each connecting unit are respectively connected to two detecting units, forming a circuit for detecting whether cracks exist in the substrate. Each detecting unit includes at least two detecting endpoints. Each connecting unit includes at least two detecting wires, with each end of one detecting wire connected to one detecting endpoint of two detecting units. The at least two detecting wires between two non-adjacent detecting units are set around outside of the installation area to form a closed loop area.
    Type: Application
    Filed: September 13, 2023
    Publication date: May 23, 2024
    Inventor: KAI-LI WANG
  • Publication number: 20240169911
    Abstract: A display substrate and a display panel. The display substrate includes: a base substrate; and a plurality of sub-pixels on the base substrate, each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a current-leakage prevention sub-circuit and a storage sub-circuit; the storage sub-circuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate and the third electrode plate are electrically connected to each other and are in different layers with respect to the base substrate, and the second electrode plate at least partially overlaps the first electrode plate and the third electrode plate in a direction perpendicular to the base substrate.
    Type: Application
    Filed: May 31, 2021
    Publication date: May 23, 2024
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Yu Feng, Li Wang
  • Publication number: 20240170490
    Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
    Type: Application
    Filed: January 29, 2024
    Publication date: May 23, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: BO TAO, Li Wang, Ching-Yang Wen, Purakh Raj Verma, Zhibiao Zhou, Dong Yin, Gang Ren, Jian Xie
  • Patent number: 11990376
    Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Peng-Wei Chu, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 11986673
    Abstract: A method for generating a radiation treatment plan is provided. The method may include determining a set of one or more optimization goals for radiation delivery by a therapeutic radiation delivery apparatus. The method may also include determining a plan for radiation delivery from a radiation source of the therapeutic radiation delivery apparatus. The radiation source may be capable of continuously rotating around a subject. The plan may include a plurality of radiation segments. Each radiation segment may be characterized by at least one parameter selected from a start angle, a stop angle, a two-dimensional segment shape, or a segment MU value such that the plurality of radiation segments satisfy the set of one or more optimization goals by superimposing at least two radiation segments from at least two different rotations into a target volume of the subject.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: May 21, 2024
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Jingjie Zhou, Li Wang, Cheng Ni, Johannes Stahl, Jonathan Maltz
  • Patent number: 11986674
    Abstract: The present disclosure relates to a system and a method. The system may include a magnetic resonance imaging (MRI) apparatus configured to acquire MRI data with respect to a region of interest (ROI) and a therapeutic apparatus configured to apply therapeutic radiation to at least one portion of the ROI. The MRI apparatus may include a plurality of main magnetic coils arranged coaxially along an axis, a plurality of shielding magnetic coils arranged coaxially along the axis, and a cryostat in which the plurality of main magnetic coils and the plurality of shielding magnetic coils are arranged.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 21, 2024
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Cheng Ni, Xingen Yu, Yanfang Liu, Jingjie Zhou, Jianfeng Liu, Li Wang, Peng Wang, Yangyang Zhang
  • Patent number: 11990951
    Abstract: A method for implementing fault diagnosis by means of a spread spectrum carrier includes the following steps: designing incident signal parameters, selecting a spread spectrum sequence for fault detection, determining a center frequency and a sequence length of a spread spectrum code, and segmenting and transforming a power carrier source signal; using the fault detection spread spectrum sequence as a carrier spread spectrum code, and performing spread spectrum modulation on the transformed power carrier source signal to generate an SSPLCR sequence; coupling the SSPLCR sequence to a cable to be tested, and when the cable works normally without failure, transmitting the SSPLCR signal to the receiving terminal via the cable; when the cable fails, reflecting the SSPLCR signal back to the transmitting terminal.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: May 21, 2024
    Assignee: NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS
    Inventors: Li Wang, Weijia Chen
  • Publication number: 20240158507
    Abstract: The present invention is directed to synergic or additive therapies comprising the administration of a VISTA antagonist and a PD-1, PD-L1 or POD-L3 antagonist; or the combination of a VISTA agonist and a -1, PD-L1 or POD-L3 agonist which combinations respectively elicit an additive or synergistic effect at promoting T cell immunity or inhibiting T cell immunity, i.e., CD4, CD8 or Th1 immunity. The agonists and antagonists may be in the same or separate compositions and may be administered together or separately administered in either order.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 16, 2024
    Inventors: Randolph J. Noelle, Li Wang, Thomas Broughton, Lorenzo F. Sempere, Janet Louise Lines
  • Publication number: 20240162898
    Abstract: A power switch device with cascode structure provides better performance with simple design. It has a normally-on device and a normally-off device coupled in series. A resistor is coupled to a control terminal of the normally-on device; and a capacitor is coupled between a control terminal of the normally-off device and the control terminal of the normally-on device.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 16, 2024
    Inventors: Vipin Pala, Panyin Liu, Li Wang, Qiang Fan, Xiangyi Yang
  • Patent number: 11984292
    Abstract: The present disclosure is related to a microwave source. The microwave source may include a cathode heater and a thermionic emitter. The cathode heater may include a first component, and a second component enclosing at least a portion of the first component. The thermionic emitter may be configured to release electrons when the thermionic emitter is heated by the cathode heater. At least a portion of the second component of the cathode heater may be in contact with the thermionic emitter.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: May 14, 2024
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Cheng Ni, Gang Pan, Zhangfan Deng, Mingyuan Song, Zongrui Sun, Haoshan Zhu, Feichao Fu, Jincheng Mei, Chengjia Yuan, Li Wang, Xiaofeng Zhang, Jianxiong Zou
  • Patent number: 11984450
    Abstract: A device includes a semiconductive fin, an isolation structure, a gate structure, dielectric spacers, and source/drain epitaxial structures. The isolation structure surrounds a bottom portion of the semiconductive fin. The gate structure is over the semiconductive fin. The dielectric spacers are on opposite sides of the semiconductive fin and over the isolation structure. The dielectric spacers include nitride. The source/drain epitaxial structures are on opposite sides of the gate structure and over the dielectric spacers. The source/drain epitaxial structures have hexagon shapes.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 11980216
    Abstract: The disclosure discloses stabilized rice aleurone and a preparation method, using the technology of classifying a rice aleurone layer by a tangential injection airflow impeller classifier combined with an ultrasonic vibrating screen for the first time, and simultaneously uses steam treatment coupled with thermal enzyme inactivation by drum drying as a stabilization method to prepare the stabilized rice aleurone for the first time. The drum drying equipment realizes the two purposes of enzyme inactivation and drying, and the method has the advantages of short process flow, simple equipment, high utilization rate, small floor space, low investment, low energy consumption and no pollution, and is suitable for industrial promotion. The stabilized rice aleurone has high nutritional value, is rich in functional ingredients, and can be used as a raw material for functional food development in industrial production and food applications.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 14, 2024
    Assignees: JIANGSU STATE FARM CEREALS INDUSTRY GROUP CO., LTD., JIANGNAN UNIVERSITY, JIANGSU PROVINCIAL AGRICULTURAL RECLAMATION AND DEVELOPMENT CO., LTD.
    Inventors: Li Wang, Hui Lu, Zhicun Xu, Zhengxing Chen, Zhaoqin Zong, Yongfu Li, Xiaoyu Feng, Jie Jiang, Congnan Zhang, Haifeng Xu, Ru Feng
  • Publication number: 20240153912
    Abstract: A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Enyong Tai, Hem P. Takiar, Li Wang, Hong Wan Ng
  • Patent number: 11978396
    Abstract: Embodiments of the present disclosure provide an array substrate and related display panel and display device. An array substrate, comprises: a substrate; a plurality of sub-pixels arranged in multiple rows and multiple columns provided on the substrate, at least one of the plurality of sub-pixels comprising pixel circuits, each of the pixel circuits comprising a driving circuit, a voltage stabilizing circuit, and a driving reset circuit, wherein the driving circuit is configured to provide a driving current to a light-emitting device, the voltage stabilizing circuit comprises a first voltage stabilizing circuit and a second voltage stabilizing circuit, the first voltage stabilizing circuit is configured to conduct a control terminal of the driving circuit with the driving reset circuit, the second voltage stabilizing circuit is configured to stabilize a voltage at the control terminal of the driving circuit, and the driving reset circuit is configured to reset the control terminal of the driving circuit.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 7, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Libin Liu, Li Wang, Yu Feng, Lujiang Huangfu
  • Publication number: 20240142147
    Abstract: The present application provides a condenser, comprising: a housing, a first heat exchange tube set, a second heat exchange tube set, and a third heat exchange tube set, a pair of first baffles, a second baffle, and a third baffle, the second heat exchange tube set and the third heat exchange tube set being arranged at two sides of the first heat exchange tube set, each of the pair of first baffles being respectively adjacent to the two sides of the first heat exchange tube set, the second baffle being adjacent to one side of the second heat exchange tube set that is close to the first heat exchange tube set, and the third baffle being adjacent to one side of the third heat exchange tube set that is close to the first heat exchange tube set, wherein the pair of first baffles, the second baffle, and the third baffle are configured to cause the first heat exchange tube set to receive a refrigerant from a refrigerant inlet, and cause the second heat exchange tube set and the third heat exchange tube set to recei
    Type: Application
    Filed: February 23, 2022
    Publication date: May 2, 2024
    Inventors: Xiuping Su, Li Wang
  • Publication number: 20240146916
    Abstract: Filtering methods, apparatus, and devices are provided. In one aspect, a filtering method includes: determining whether enhanced adaptive leveling filtering is enabled for a current adaptive leveling filtering unit; if it is determined that the enhanced adaptive leveling filtering is enabled for the current adaptive leveling filtering unit, performing adaptive leveling filtering on the current adaptive leveling filtering unit by using a first filter; if it is determined that the enhanced adaptive leveling filtering is disabled for the current adaptive leveling filtering unit, performing adaptive leveling filtering on the current adaptive leveling filtering unit by using a second filter. The first filter includes a centrosymmetric filter with a 7*7 cross shape plus a 5*5 square shape, and the second filter includes a centrosymmetric filter with a 7*7 cross shape plus a 3*3 square shape.
    Type: Application
    Filed: March 2, 2022
    Publication date: May 2, 2024
    Inventors: Dongping PAN, Yucheng SUN, Fangdong CHEN, Li WANG
  • Publication number: 20240141342
    Abstract: A method for ameliorating or treating a malignant tumor by administering a therapeutically effective amount of a formulation containing RNAi agents. A formulation for use in distributing RNAi molecules targeted to a human GST-? for treating a malignant tumor in a subject. The formulation may include nanoparticles composed of an ionizable lipid, a DSPE lipid, and additional lipids. A drug product may be made by lyophilization of the formulation.
    Type: Application
    Filed: April 11, 2023
    Publication date: May 2, 2024
    Inventors: Bharat Majeti, Jean-Pierre Clamme, Li Wang, Roger C. Adami, Wenbin Ying
  • Publication number: 20240145569
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia YEO, Sung-Li WANG, Chi On CHUI, Jyh-Cherng SHEU, Hung-Li CHIANG, I-Sheng CHEN
  • Publication number: 20240144430
    Abstract: A computing system performs artificial-intelligence (AI) super-resolution (SR). The computing system includes multiple processors, which further includes a graphics processing unit (GPU) and an AI processing unit (APU). The computing system also includes a memory to store AI models. When detecting an indication that the loading of the GPU exceeds a threshold, the processors reduce the resolution of a video output from the GPU in response to the indication. One of the AI models is selected based on graphics scenes in the video and the respective power consumption estimates of the AI models. The processors then perform AI SR operations on the video using the selected AI model to restore the resolution of the video for display.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 2, 2024
    Inventors: Chien-Nan Lin, You-Ming Tsao, Yung-Hsin Chu, An-Li Wang
  • Publication number: 20240144870
    Abstract: Provided are a pixel circuit, a driving method, and a display device. The pixel circuit includes a light-emitting element, drive circuit, control circuit, first initialization circuit, first light-emitting control circuit and second light-emitting control circuit, wherein the control circuit causes a control terminal of the drive circuit to be electrically connected to a connection node under the control of a first scanning signal; the first initialization circuit writes a first initial voltage to the connection node under the control of a reset control signal; the first light-emitting control circuit causes a first voltage terminal to be conductively connected to a first terminal of the drive circuit under the control of a first light-emitting control signal; the second light-emitting control circuit causes a second terminal of the drive circuit to be conductively connected to a first electrode of the light-emitting element under control of a second light-emitting control signal.
    Type: Application
    Filed: July 12, 2022
    Publication date: May 2, 2024
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Wang, Libin Liu