Patents by Inventor An-Li WANG

An-Li WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11913551
    Abstract: Housing seals and methods seal off a housing interior from a housing exterior. The housing seals and methods comprise an elastic adhesive strip that is arranged between a first housing element and a second housing element, wherein the adhesive strip comprises a first end portion having a first edge face, and a second end portion having a second edge face, wherein the adhesive strip and is arranged between the first housing element and the second housing element in such a way that the first and second edge faces lie substantially in a plane, the adhesive strip is arranged between the first housing element and the second housing element in a closed circulation, and the first edge face of the adhesive strip is in contact with the second edge face of the adhesive strip and forms a sealing gap.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: February 27, 2024
    Assignee: TESA SE
    Inventors: Deniz Nick Akin, Wilhelm Watzke, Li Wang, Kim Elsenbach
  • FAN
    Publication number: 20240060505
    Abstract: A fan, comprising blades (102), an upper hub (111), and a lower hub (112). Each blade (102) comprises a connecting part (211). The connecting part (211) is clamped between a lower surface of the upper hub (111) and an upper surface of the lower hub (112). The lower surface of the upper hub (111) is provided with an upper hub connecting area, and the upper surface of the lower hub (112) is provided with a lower hub connecting area. An upper surface and a lower surface of the connecting part (211) are separately provided with a junction surface extending from the connecting part (211). The lower surface of the upper hub (111) and the upper surface of the lower hub (112) are separately provided with a matching surface matching the junction surface.
    Type: Application
    Filed: July 23, 2021
    Publication date: February 22, 2024
    Inventors: Chenggang Wu, Bin Yuan, Xiaokui Ma, Li Wang, Jian Zhu
  • Publication number: 20240058614
    Abstract: A cardiac pacing threshold acquisition method, a pacing control method and apparatus, and a medical device. The acquisition method comprises: in a pacing test phase, using an initial pacing frequency and an initial pacing output to perform pacing on a patient; under the pacing operation, measuring first response information of the ventricle of a patient to the initial pacing frequency; according to whether an R wave is present in the first response information, adjusting pulse voltage amplitude or pulse width of the initial pacing frequency so as to obtain a cardiac pacing threshold corresponding to the patient.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 22, 2024
    Inventor: Li Wang
  • Patent number: 11908833
    Abstract: A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Enyong Tai, Hem P. Takiar, Li Wang, Hong Wan Ng
  • Publication number: 20240055485
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, wherein the second epitaxial layer has a first dopant concentration, and a third epitaxial layer having sidewalls enclosed by the second epitaxial layer, wherein the third epitaxial layer has a second dopant concentration higher than the first dopant concentration. The semiconductor device structure also includes a source/drain cap layer disposed above and in contact with the second epitaxial layer and the third epitaxial layer, wherein the source/drain cap layer has a third dopant concentration higher than the second dopant concentration, and a silicide layer disposed above and in contact with the source/drain cap layer.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Shuen-Shin LIANG, Sung-Li WANG, Yi-Ying LIU
  • Publication number: 20240055491
    Abstract: A semiconductor device includes parallel channel members, a gate structure, source/drain features, a silicide layer, and a source/drain contact. The parallel channel members are spaced apart from one another. The gate structure is wrapping around the channel members. The source/drain features are disposed besides the channel members and at opposite sides of the gate structure. The silicide layer is disposed on and in direct contact with the source/drain features. The source/drain contact is disposed on the silicide layer, wherein the source/drain contact includes a first source/drain contact and a second source/drain contact stacked on the first source/drain contact, and the second source/drain contact is separate from the silicide layer by the first source/drain contact.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hung Chu, Shuen-Shin Liang, Chung-Liang Cheng, Sung-Li Wang, Chien Chang, Harry CHIEN, Lin-Yu Huang, Min-Hsuan Lu
  • Patent number: 11896412
    Abstract: A method and a device of controlling the position of the X-ray tube of a computed tomography (CT) system may include: acquiring an AP signal output by an AP sensor of the CT system, an IP signal output by an IP sensor and encoder data output by a motor, determining a homing positioning signal AP0 of the AP signal based on the AP signal and the IP signal, where the homing positioning signal AP0 is used to determine the starting point of the period of rotation of the X-ray tube, utilizing the encoder data to calculate the encoder data containing AP signal based on the determined homing positioning signal AP0, where the encoder data containing AP signal is the AP signal processed by use of the encoder data, and controlling the position of the X-ray tube based on the encoder data containing AP signal.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: February 13, 2024
    Assignee: Siemens Healthcare GmbH
    Inventors: Ying Li Wang, Jin Hua Ding, Jian Zhang, Jia Peng Zhu
  • Patent number: 11896836
    Abstract: A delivery device, a cardiac pacing device and a fixation structure are disclosed. The fixation structure includes a casing, a driving member and an elastic member. The casing has a first internal cavity and a slot, and the driving member is partially received in the first internal cavity in such a manner that one end of the driving member protrudes out of the first internal cavity from a proximal end thereof and is detachably connected to the driving sheath. The elastic member is accommodated in the first internal cavity in such a manner that its one end is coupled to the driving member and the other end extends outwardly from the driving member and is inserted in the slot. The driving member is configured for fitted connection with the casing while being able to move in an axial direction of the casing to drive the elastic member to move in the slot, thereby causing the elastic member to protrude out of or move back into the slot.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: February 13, 2024
    Assignee: MICROPORT SOARING CRM (SHANGHAI) CO., LTD.
    Inventors: Zhijun Cheng, Grace Jang, Li Wang
  • Patent number: 11903279
    Abstract: There is provided a display substrate, in which, a first reference voltage line and a first reference voltage auxiliary line, which extend in different directions, are respectively disposed in one of a second wiring layer, a third wiring layer and a fourth wiring layer, a second reference voltage line extends in the same direction as the first reference voltage auxiliary line, the first reference voltage auxiliary line is electrically coupled to the first reference voltage line through via holes in an insulating layer therebetween, via a coupling line extending in the same direction as the first reference voltage line, the first reference voltage auxiliary line and the first reference voltage line provide a reset voltage to a first electrode of a first capacitor, and the second reference voltage line provides a reset voltage to a pixel electrode in a pixel electrode layer. A display device is further provided.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 13, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Wang, Libin Liu
  • Patent number: 11900883
    Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: a second noise reduction control circuit. The second noise reduction control circuit includes: a first control circuit, configured to transmit a first voltage to a second noise reduction control node; a first coupling circuit, configured to store a level of the second noise reduction control node and adjust the level of the second noise reduction control node; a second coupling circuit, configured to reduce an adjustment magnitude of the first coupling circuit in case of adjusting the level of the second noise reduction control node; a transmission circuit, configured to connect the first noise reduction control node and the second noise reduction control node; and a storage circuit, configured to store the level of the first noise reduction control node.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: February 13, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangliang Shang, Can Zheng, Jiangnan Lu, Yuhan Qian, Li Wang, Libin Liu, Shiming Shi, Dawei Wang
  • Publication number: 20240041482
    Abstract: The present invention relates to the field of medical instruments, more particularly to a pulse balloon and use thereof. The pulse balloon comprises a balloon body and an inner tube, wherein the balloon body comprises an insulating layer and a balloon wall. The insulating layer is arranged on the balloon body, when the balloon body operates, the balloon body is filled with an electrolyte so that an electrode releases high-pulse piezoelectricity to generate pulses, the electrolyte spreads to drive the vibration of the balloon, so that most of electrical energy is converted into mechanical energy to break down a calcified area of a blood vessel, and the residual high voltage is blocked by the insulating layer.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 8, 2024
    Inventors: Philip Li WANG, Chenzhao ZHANG, Xinfeng LIANG, Tao CAI, Junyi WANG
  • Publication number: 20240045993
    Abstract: Privacy preservation model training includes a plurality of iterative update rounds performed on a model held by a data party of a plurality of data parties participating in training to obtain model data, which includes first shared data and local data corresponding to a shared portion and a dedicated portion of the model, respectively. The iterative training adds a perturbation to the first shared data to perform privacy preservation on at least the first shared data. The first shared data is transmitted to a server, which determines, based on first shared data of the plurality of data parties, second shared data. The shared portion of the model is updated based on the second shared data returned by the server. A next iterative update round is performed based on an updated model or using the updated model as a final model.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Applicant: Alipay (Hangzhou) Information Technology Co., Ltd.
    Inventors: Huiwen Wu, Cen Chen, Li Wang
  • Publication number: 20240046160
    Abstract: Implementations of this specification disclose methods and systems for training a privacy protection model. In an implementation, a method comprising: performing one or more times of iterative training on the model based on a training sample held by the data party to obtain model data, transmitting the first shared data to a server for the server to determine second shared data based on the first shared data, receiving the second shared data from the server, updating the shared portion of the model based on the second shared data to obtain an updated shared portion, and generating, based on the updated shared portion, an updated model for performing a next one of the plurality of iterative updates in response to determining that the next one of the plurality of iterative updates is not a last one of the plurality of iterative updates.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 8, 2024
    Applicant: Alipay (Hangzhou) Information Technology Co., Ltd.
    Inventors: Huiwen Wu, Cen Chen, Li Wang
  • Publication number: 20240048726
    Abstract: Decoding methods and encoding methods based on an adaptive intra refresh mechanism and related devices are provided. In one aspect, a decoding method includes: receiving a bit stream of a current frame; and determining whether the current frame supports an adaptive intra refresh technology. The determining comprises one of if there is extension data in the bit stream of the current frame and the extension data carries an adaptive intra refresh video extension identifier (ID), obtaining virtual boundary position information carried in the extension data, and determining whether the current frame supports an adaptive intra refresh technology based on the virtual boundary position information; or if there is no adaptive intra refresh video extension ID in the extension data in the bit stream of the current frame, determining that the current frame does not support the adaptive intra refresh technology.
    Type: Application
    Filed: March 10, 2022
    Publication date: February 8, 2024
    Inventors: Liang WEI, Fangdong CHEN, Li WANG
  • Patent number: 11894438
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Sung-Li Wang, Chi On Chui, Jyh-Cherng Sheu, Hung-Li Chiang, I-Sheng Chen
  • Patent number: 11893938
    Abstract: Provided are a pixel circuit, a display panel and a display apparatus. The pixel circuit includes: a first resetting switching transistor, a first data writing switching transistor, a storage capacitor, a first compensation capacitor, a second compensation capacitor, and a driving transistor; the first resetting switching transistor includes a first switching sub-transistor and a second switching sub-transistor connected in series, and the first data writing switching transistor includes a third switching sub-transistor and a fourth switching sub-transistor connected in series. The first compensation capacitor and the second compensation capacitor are used to enable a voltage Vn1? of the first node to be smaller than a voltage Vn3? of the third node and larger than a voltage Vn4? of the fourth node in a light-emitting stage.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: February 6, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Wang, Can Zheng
  • Patent number: 11894437
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chih-Chien Chi, Chien-Shun Liao, Keng-Chu Lin, Kai-Ting Huang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang, Cheng-Wei Chang
  • Publication number: 20240038595
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Jhih-Rong HUANG, Yi-Bo LIAO, Shuen-Shin LIANG, Min-Chiang CHUANG, Sung-Li WANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240038550
    Abstract: The present disclosure discloses a manufacturing method of an electronic device. A seed layer is formed on a substrate. After patterning the seed layer to form a plurality of sub-seed layers and a plurality of conductive lines, a metal layer is formed on a plurality of the sub-seed layers. The sub-seed layers include a first sub-seed layer and a second sub-seed layer, and the first sub-seed layer and the second sub-seed layer are separated from each other.
    Type: Application
    Filed: October 20, 2022
    Publication date: February 1, 2024
    Applicant: InnoLux Corporation
    Inventors: Chin-Lung TING, Cheng-Chi WANG, Yu-Jen CHANG, Ju-Li WANG
  • Patent number: D1013630
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: February 6, 2024
    Inventor: Li Wang