Patents by Inventor An Liu
An Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250103911Abstract: An electricity consumption pattern classification method involves, initially, reading multiple training electricity consumption data sets. After which, the method includes performing a first clustering phase with a first machine learning clustering algorithm according to the electricity consumption characteristics of the training electricity consumption data sets, and generating multiple first-level data groups. Then, second-level feature values of the training electricity consumption data sets are generated with a feature extraction algorithm, and a second clustering phase with a second machine learning clustering algorithm is performed to generate second-level data groups under the first-level data groups. The classification result of an unclassified data set is determined according to the average similarity between the unclassified data set and each second-level data group.Type: ApplicationFiled: October 26, 2023Publication date: March 27, 2025Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Su-An LIU, Kuei-Chun CHIANG, Yung-Chieh HUNG
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Publication number: 20250089332Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: ApplicationFiled: November 27, 2024Publication date: March 13, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN
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Patent number: 12218074Abstract: In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.Type: GrantFiled: June 9, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
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Patent number: 12199393Abstract: A method of assembling a waterproof structure includes the following operations. Connect a first input/output connector of a circuit board to a first positioning fixture. A first elastic adhesive is combined with a first rigid board. An end of the first positioning fixture away from the first input/output connector is passed out of the first rigid board, and the first input/output connector and the first elastic adhesive are separated on two sides of the first rigid board. The circuit board is arranged in the casing, wherein the first positioning fixture is inserted from the first input/output opening on the first wall inside the casing, so that the first elastic adhesive adheres the first rigid board to the first wall of the casing, and the first elastic adhesive fills a spacing between the first positioning fixture and the first input/output opening.Type: GrantFiled: June 7, 2022Date of Patent: January 14, 2025Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATIONInventors: Chia-Chen Chen, Yin-Chang Cheng, Tang-An Liu, Yung-Hung Chu, Chi-Zen Peng
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Publication number: 20250015007Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.Type: ApplicationFiled: July 6, 2023Publication date: January 9, 2025Inventors: Yu-Chung Lai, Ying-Yao Lai, Chen-Chiu Huang, Hsiang-Ku Shen, Dian-Hau Chen, Kuo-An Liu, Tzu-Ting Liu
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Publication number: 20250015278Abstract: Disclosed is an all-solid-state lithium battery, characterized in that an anode of the all-solid-state lithium battery comprises solid lithium metal, a solid-state electrolyte of the all-solid-state lithium battery comprises lithium lanthanum zirconium oxide, and a joint interface region between the anode and the solid-state electrolyte contains at least lithium nitride and lithium alloy.Type: ApplicationFiled: September 15, 2023Publication date: January 9, 2025Applicant: CPC CORPORATION, TAIWANInventors: Shih-An LIU, Yu-Kai LIAO, Shu-Fen HU, Kevin IPUTERA, Ru-Shi LIU, Jui-Hsiung HUANG
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Patent number: 12183805Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: GrantFiled: May 28, 2021Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
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Patent number: 12174545Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: GrantFiled: July 28, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yu Chen, Sagar Deepak Khivsara, Kuo-An Liu, Chieh Hsieh, Shang-Chieh Chien, Gwan-Sin Chang, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 12160216Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a heat source on the substrate, and a heat pipe. The heat pipe includes a plurality of bumps that extend from the heat pipe towards the substrate but do not come into contact with the substrate. The bumps are configured to help mitigate radio frequency interference in the electronic device. More specifically, the bumps can be configured to provide a resonant frequency in a specific radio frequency band and act as a radio frequency filter.Type: GrantFiled: December 15, 2020Date of Patent: December 3, 2024Assignee: Intel CorporationInventors: Kae-An Liu, Jaejin Lee, David W. Browning
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Publication number: 20240383772Abstract: A lithium nickel manganese oxide core-shell material, comprising a core, composed of a first lithium nickel manganese oxide material; and a shell, covering the core and composed of a second lithium nickel manganese oxide material, wherein the first lithium nickel manganese oxide material and the second lithium nickel manganese oxide material contain manganese and nickel, and the ratio of manganese and nickel in the first lithium nickel manganese oxide material is different from the ratio of manganese and nickel in the second lithium nickel manganese oxide material.Type: ApplicationFiled: September 13, 2023Publication date: November 21, 2024Applicant: CPC CORPORATION, TAIWANInventors: Shih-An LIU, Jen-Hsien HUANG, Jui-Hsiung HUANG
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Publication number: 20240379593Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.Type: ApplicationFiled: July 12, 2024Publication date: November 14, 2024Inventors: Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang, Zhiqiang Wu, Dian-Hau Chen
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Publication number: 20240336052Abstract: A mat and a method for manufacturing the same are provided. The mat includes a first foam layer, a second foam layer and a third foam layer. The first foam layer has a first hardness and a first porosity. The second foam layer is connected with the first foam layer and has a second hardness and a second porosity larger than the first porosity. The third foam layer is connected with the second foam layer and has a third hardness and a third porosity smaller than the first porosity. The second foam layer includes a first connecting surface facing the first foam layer and a second connecting surface facing the third foam layer. The contact area between the first connecting surface and the first foam layer is different from the contact area between the second connecting surface and the third foam layer.Type: ApplicationFiled: June 15, 2024Publication date: October 10, 2024Inventors: Bruce A. Thrush, Tung-An Liu
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Patent number: 12087714Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.Type: GrantFiled: January 31, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang, Zhiqiang Wu, Dian-Hau Chen
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Publication number: 20240296709Abstract: An electronic device includes a housing and a drainage structure. The drainage structure includes a shoulder surrounding wall connected to a top end of the housing, and an outer surrounding wall extending from the shoulder surrounding wall. The shoulder surrounding wall has opposite rear and front end portions, and is inclined with the front end portion lower than the rear end portion. The housing defines a receiving space and has a front housing wall that has a first slanted wall portion formed with an image-capturing opening. An angle is formed between a central line normal to the first slanted wall portion and extending through the image-capturing opening and a reference line, and is smaller than 90 degrees. Atop cover unit closes the receiving space. An image-capturing module is disposed in the receiving space.Type: ApplicationFiled: March 1, 2024Publication date: September 5, 2024Inventor: Che-An LIU
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Publication number: 20240256289Abstract: Systems, apparatus, and methods for “fast” wake-up using virtualized addresses. Action cameras need to conserve power most of the time, but also be immediately responsive to catch action when it happens. Unfortunately, most general-purpose operating systems (e.g., Linux-based) lock up the processor during boot-up. Empirically, an OS boot process might take between 6-7 seconds from start to finish, even in highly streamlined boot sequences. This is undesirable, especially where one device (e.g., a smart phone) triggers an action camera to capture an image. Various embodiments of the present disclosure create “virtual action addresses” that directly expose interrupts as addressable space (via a Bluetooth Low Energy (BLE) network). In one such example, the interrupts trigger a capture or other action. The action camera can immediately service the interrupts with its real-time operating system (RTOS) while the general-purpose OS is booting up.Type: ApplicationFiled: February 1, 2023Publication date: August 1, 2024Applicant: GoPro, Inc.Inventors: Gregory Paul Stewart, Dick Ji-An Liu, Timothy Ryan Camise, Neal Nai-Chang Yu
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Patent number: 12011910Abstract: A mat and a method for manufacturing the same are provided. The mat includes a first foam layer, a second foam layer and a third foam layer. The first foam layer has a first hardness and a first porosity. The second foam layer is connected with the first foam layer and has a second hardness and a second porosity larger than the first porosity. The third foam layer is connected with the second foam layer and has a third hardness and a third porosity smaller than the first porosity. The second foam layer includes a first connecting surface facing the first foam layer and a second connecting surface facing the third foam layer. The contact area between the first connecting surface and the first foam layer is different from the contact area between the second connecting surface and the third foam layer.Type: GrantFiled: August 19, 2022Date of Patent: June 18, 2024Assignee: The Parallax Group International, LLCInventors: Bruce A. Thrush, Tung-An Liu
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Patent number: 11992911Abstract: A tool changing mechanism includes a tool base housing, a mandrel disposed therein and having a chamber and a keyway provided axially, and first and second linked units. A first shoulder portion is provided at an end of the keyway, and pulling jaws are disposed at the other end. The first linked unit has a first pulling rod, an end of which has an external thread, and the other end has a connecting portion driven by a pneumatic cylinder. The second linked unit has a second pulling rod, an end of which has an internal thread, and a pressing head is disposed at the other end. The second pulling rod has a sliding key located in the keyway. The first pulling rod is screwed into the second pulling rod, and the relative screwing rotation therebetween attains tool pulling for fixing or tool loosening for removing the cutting tool.Type: GrantFiled: September 30, 2021Date of Patent: May 28, 2024Assignee: PRECISION MACHINERY RESEARCH & DEVELOPMENT CENTERInventors: Chia-Hsuan Cho, Yu-An Liu
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Publication number: 20240159552Abstract: Systems and methods for determining vehicle vocation are provided. The method involves operating at least one processor to: retrieve telematics data associated with a vehicle, the telematics data originating from a telematics device installed in the vehicle; process the telematics data to extract a plurality of feature datasets, the plurality of feature datasets including: a first dataset associated with distances traveled by the vehicle; a second dataset associated with stops completed by the vehicle; and a third dataset associated with round trips performed by the vehicle; apply a plurality of trained cluster models to the plurality of feature datasets to determine a plurality of vocation probabilities; and determine the vocation of the vehicle based on the plurality of vocation probabilities.Type: ApplicationFiled: October 10, 2023Publication date: May 16, 2024Inventors: Chien An Liu, Natalie Joy Smith
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Publication number: 20240161606Abstract: Disclosed herein are systems and methods for identifying and ranking traffic bottlenecks.Type: ApplicationFiled: November 6, 2023Publication date: May 16, 2024Inventors: Yunfei Ma, Chien An Liu
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Publication number: 20240096818Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.Type: ApplicationFiled: April 20, 2023Publication date: March 21, 2024Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Kuo-An Liu, Ching-Huang Wang, C.T. Kuo, Tien-Wei Chiang